PIC18F1320-H/ML Microchip Technology, PIC18F1320-H/ML Datasheet - Page 160
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F1320-H/ML
Manufacturer Part Number
PIC18F1320-H/ML
Description
IC MCU 8BIT 8KB FLASH 28QFN
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F1220-ISO.pdf
(308 pages)
Specifications of PIC18F1320-H/ML
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
28-VQFN Exposed Pad
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F1220/1320
The analog reference voltage is software selectable to
either the device’s positive and negative supply voltage
(AV
RA3/AN3/V
The A/D converter has a unique feature of being able
to operate while the device is in Sleep mode. To oper-
ate in Sleep, the A/D conversion clock must be derived
from the A/D’s internal RC oscillator.
The output of the sample and hold is the input into the
converter, which generates the result via successive
approximation.
FIGURE 17-1:
DS39605F-page 158
DD
Note 1: I/O pins have diode protection to V
and AV
REF
Converter
+ and RA2/AN2/V
10-bit
SS
A/D
), or the voltage level on the
Reference
Voltage
A/D BLOCK DIAGRAM
REF
- pins.
V
V
REFH
REFL
(Input Voltage)
VCFG1:VCFG0
V
AIN
DD
and V
x0
x1
1x
0x
AV
SS
.
DD
A device Reset forces all registers to their Reset state.
This forces the A/D module to be turned off and any
conversion in progress is aborted.
Each port pin associated with the A/D converter can be
configured as an analog input, or as a digital I/O. The
ADRESH and ADRESL registers contain the result of
the A/D conversion. When the A/D conversion is com-
plete, the result is loaded into the ADRESH/ADRESL
registers, the GO/DONE bit (ADCON0 register) is
cleared and A/D Interrupt Flag bit, ADIF, is set. The block
diagram of the A/D module is shown in Figure 17-1.
AV
SS
CHS2:CHS0
111
110
101
100
011
010
001
000
© 2007 Microchip Technology Inc.
AV
DD
AN6
AN5
AN4
AN3/V
AN2/V
AN1
AN0
(1)
REF
REF
+
-
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