LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 7

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
PFU Blocks
The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arith-
metic, Distributed RAM and Distributed ROM functions.
Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec-
tions to and from PFU blocks are from routing. There are 53 inputs and 25 outputs associated with each PFU block.
Figure 2-2. PFU Diagram
Slice
Each slice contains two LUT4 lookup tables feeding two registers (programmed to be in FF or Latch mode), and
some associated logic that allows the LUTs to be combined to implement 5, 6, 7 and 8 Input LUTs (LUT5, LUT6,
LUT7 and LUT8). There is control logic to perform set/reset functions (programmable as synchronous/asynchro-
nous), clock select, chip-select and wider RAM/ROM functions. Figure 2-3 shows an overview of the internal logic
of the slice. The registers in the slice can be configured for positive/negative and edge/level clocks.
There are 14 input signals: 13 signals from routing and one from the carry-chain (from adjacent slice or PFU).
There are seven outputs: six to routing and one to carry-chain (to adjacent PFU). Table 2-1 lists the signals associ-
ated with each slice.
Latch
FF/
LUT4 &
CARRY
D
Slice 0
Latch
FF/
LUT4 &
CARRY
D
Latch
FF/
LUT4 &
CARRY
D
Slice 1
Latch
FF/
LUT4 &
CARRY
D
Routing
Routing
From
2-3
To
Latch
FF/
CARRY
LUT4 &
D
Slice 2
Latch
FF/
CARRY
LUT4 &
D
LatticeSC/M Family Data Sheet
Latch
FF/
CARRY
LUT4 &
D
Slice 3
Latch
FF/
LUT4 &
CARRY
D
Architecture