LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 236

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
August 2007
March 2007
(cont.)
Date
Version
(cont.)
01.5
01.6
Characteristics (cont.)
DC and Switching
DC and Switching
Pin Information
Characteristics
Pin Information
Architecture
Section
General
Updated LatticeSC Internal Timing Parameters with ispLEVER 6.1 SP1
results.
Updated t
Updated LatticeSC Family Timing Adders with ispLEVER 6.1 SP1
results.
Updated PLL specifications to expand frequency range down to 2 MHz
and break out jitter for the different ranges.
Added footnote to sysCLOCK PLL Timing table specifying the condi-
tions for the jitter measurements.
Added t
Added footnote to sysCLOCK DLL Timing table specifying the condi-
tions for the jitter measurements.
Added sysCONFIG Master Parallel Configuration Mode and sysCON-
FIG SPI Port to LatticeSC sysCONFIG Port Timing table.
Updated Pin Information Summary with SC40 information.
Updated LFSC25 Logic Signal Connections: FF1020 with SC40 infor-
mation.
Updated LFSC80 Logic Signal Connections: FC1152 with SC40 infor-
mation.
Changed references of "HDC" to "HDC/SI".
Changed references of "LDCN" to "LDCN/SCS".
Changed references of "BUSYN/RCLK" to "BUSYN/RCLK/SCK".
Changed references of "RDCFGN" to "TSALLN".
Changed references of "TDO/RDDATA" to "TDO".
Updated text in Ripple Mode section.
Added information to Global Set/Reset.
Added information for Spread Spectrum Clocking
Modified information for PLL/DLL Cascading. DLL to PLL is now sup-
ported.
Modified AIL Block text and figure.
Modified Figure 2-20 DDR/Shift Register Block.
Added Information to Hot Socketing.
Added new information for I/O Architecture Rules.
Added information to SERDES Power Supply Sequencing Require-
ments.
Added footnote to Hot Socketing Specifications table.
Modified Initialization and Standby Supply Current table.
Modified GSR Timing table.
Modified sysCLOCK DLL Timing table to include I
Deleted Readback Timing information from sysCONFIG Port Timing
table.
Modified data in External Switching Characteristics table.
Added information to the Signal Descriptions table for HDC/SI, LDCN/
SCS.
Added footnote to Signal Descriptions table.
Modified Description for signal BUSYN/RCLK/SCK.
Modified data in Pin Information Summary and device-specific Pinout
Information tables.
7-4
DLL
FDEL
specification to sysCLOCK DLL Timing table.
and t
CDEL
specifications.
Change Summary
LatticeSC/M Family Data Sheet
Revision History
DUTY.