LFSC3GA15E-7FN256C Lattice, LFSC3GA15E-7FN256C Datasheet - Page 28

• Manufacturer Part Number: LFSC3GA15E-7FN256C
• Description: IC FPGA 15.2KLUTS 256FPBGA
• Manufacturer: Lattice

Specifications of LFSC3GA15E-7FN256C

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
PURESPEED I/O Buffer Banks
LatticeSC devices have seven PURESPEED I/O buffer banks; each is capable of supporting multiple I/O stan-
dards. Each PURESPEED I/O bank has its own I/O supply voltage (V
V
banks and their associated supplies. Table 2-7 lists the maximum number of I/Os per bank for the whole LatticeSC
family.
In the LatticeSC devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS, PCI33 and PCIX33)
are powered using V
supply, and a V
single-ended output buffers to enhance buffer performance.
Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer-
enced input buffers. In the LatticeSC devices any I/O pin in a bank can be configured to be a dedicated reference
voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages.
Differential drivers have user selectable internal or external bias. External bias is brought in by the VREF1 pin in the
bank. External bias for differential buffers is needed for applications that requires tighter than standard output com-
mon mode range.
Since a bank can have only one external bias circuit for differential drivers, LVDS and RSDS differential outputs can
be mixed in a bank but not with HYPT (HyperTransport).
If a differential driver is configured in a bank, one pin in that bank becomes a DIFFR pin. This DIFFR pin must be
connected to ground via an external 1K +/-1% ohm resistor. Note that differential drivers are not supported in
banks 1, 4 and 5.
In addition, there are dedicated Terminating Supply (V
ways to perform parallel terminations. These V
some packages. When VTT termination is not required, or used to provide the common mode termination voltage
(VCMT), these pins can be left unconnected on the device. If the internal or external VCMT function for differential
input termination is used, the VTT pins should be unconnected and allowed to float.
There are further restrictions on the use of V
this data sheet.
REF2
resources allowing each bank to be completely independent from each other. Figure 2-26 shows the seven
CCAUX
CCIO
supply that power all differential and referenced buffers. VCCAUX also powers a predriver of
. In addition to the bank V
TT
pins, for additional details refer to technical information at the end of
TT
CCIO
pins are available in banks 2-7, these pins are not available in
TT
supplies, the LatticeSC devices have a V
2-24
) pins to be used as terminating voltage for one of the two
CCIO
), and two voltage references V
LatticeSC/M Family Data Sheet
CC
core logic power
Architecture
REF1
and