LFSC3GA15E-6FN900I Lattice, LFSC3GA15E-6FN900I Datasheet
LFSC3GA15E-6FN900I
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... LatticeSC/M Family Data Sheet DS1004 Version 02.1, June 2008 ...
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... Block RAM © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Note: The information in this preliminary data sheet is by definition not final and subject to change. Please consult the Lat- tice website and your local Lattice sales manager to ensure you have the latest information regarding the specifications for these products as you make critical design decisions. ...
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... The ispLEVER tool uses the synthesis tool output along with the constraints from its floor planning tools to place and route the design in the LatticeSC device. The ispLEVER tool extracts the timing from the routing and back- annotates it into the design for timing verification. ...
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... FPGA logic. The LatticeSC devices use 1.2V as their core voltage operation with 1.0V operation also possible. © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... I/O Cell (PIC) includes PURESPEED I/O Interface Each PIC contains four Programmable I/Os (PIO) Three PICs per four PFUs sysCLOCK Analog PLLs LatticeSC/M Family Data Sheet Quad SERDES 2-2 Architecture Physical Coding Sublayer (PCS) Structured ASIC Block (MACO) Programmable Function Unit (PFU) ...
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... Lattice Semiconductor PFU Blocks The core of the LatticeSC devices consists of PFU blocks. The PFUs can be programmed to perform Logic, Arith- metic, Distributed RAM and Distributed ROM functions. Each PFU block consists of four interconnected slices, numbered 0-3 as shown in Figure 2-2. All the interconnec- tions to and from PFU blocks are from routing ...
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... LUT4 output register bypass signals Q0, Q1 Register Outputs OFX0 Output of a LUT5 MUX OFX1 Output of a LUT6, LUT7, LUT8 FCO For the right most PFU the fast carry chain output 2-4 Architecture LatticeSC/M Family Data Sheet Slice OFX1 FF/ Latch To Routing OFX0 ...
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... LUTs and Slices, a variety of different memories can be constructed. The Lattice design tools support the creation of a variety of different size memories. Where appropriate, the soft- ware will construct these using distributed memory primitives that represent the capabilities of the Slice. Table 2-3 shows the number of Slices required to implement different distributed RAM primitives ...
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... LUT 7x1 or MUX 16x1 x 1 Routing There are many resources provided in the LatticeSC devices to route signals individually or as busses with related control signals. The routing resources consist of switching circuitry, buffers and metal interconnect (routing) seg- ments. The inter-PFU connections are made with x1 (spans two PFU), x2 (spans three PFU) and x6 (spans seven PFU) resources. The x1 and x2 connections provide fast and effi ...
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... PLL Primary Clock Routing The clock routing structure in LatticeSC devices consists of 12 Primary Clock lines per quadrant. The primary clocks are generated from 64:1 MUXs located in each quadrant. Three of the inputs to each 64:1 MUX comes from local routing, one is connected to GND and rest of the 60 inputs are from the primary clock sources. Figure 2-6 shows this clock routing ...
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... Edge Clocks LatticeSC devices have a number of high-speed edge clocks that are intended for use with the PIOs in the imple- mentation of high-speed interfaces. There are eight edge clocks per bank for the top and bottom of the device. The left and right sides have eight edge clocks per side for both banks located on that side ...
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... The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is Bank 1 Edge clock Bank 5 Bank 4 S/R S/R Register chain to synchronize LSR to clock input 2-9 Architecture LatticeSC/M Family Data Sheet SERDES Divided clock S/R S/R ELSR ...
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... The sysCLOCK PLLs provide the ability to synthesize clock frequencies. Each PLL has four dividers associated with it: input clock divider, feedback divider and two clock output dividers. The input divider is used to divide the input clock signal, while the feedback divider is used to multiply the input clock signal. LatticeSC/M Family Data Sheet CLK0 CLK1 ...
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... Digital Locked Loop (DLLs) In addition to PLLs, the LatticeSC devices have DLLs per device. DLLs assist in the management of clocks and strobes. DLLs are well suited to applications where the clock may be stopped or transferring jitter from input to output is important, for example forward clocked interfaces. PLLs are good for applications requiring the lowest out- put jitter or jitter fi ...
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... PFD CLKFB ALUHOLD UDDCNTL RSTN PLL/DLL Cascading The LatticeSC devices have been designed to allow certain combinations of PLL and DLL cascading. The allow- able combinations are as follows: • PLL to PLL • PLL to DLL • DLL to DLL • DLL to PLL DLLs are used to shift the clock in relation to the data for source synchronous inputs. PLLs are used for frequency synthesis and clock generation for source synchronous interfaces. Cascading PLL and DLL blocks allows applica- tions to utilize the unique benefi ...
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... The sysMEM block can implement single port, true dual port, pseudo dual port or FIFO memories. Dedicated FIFO support logic allows the LatticeSC devices to efficiently implement FIFOs without consuming LUTs or routing resources for flag generation. Each block can be used in a variety of depths and widths as shown in Table 2-5. ...
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... True Dual Port 4,096 x 4 2,048 x 9 1,024 x 18 16,384 x 1 8,192 x 2 4,096 x 4 Pseudo Dual Port 2,048 x 9 1,024 x 18 512 x 36 16,384 x 1 8,192 x 2 4,096 x 4 FIFO 2,048 x 9 1,024 x 18 512 x 36 2-14 Architecture LatticeSC/M Family Data Sheet ...
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... RESET pin is always asynchronous. Note that there are no reset restrictions if the EBR synchronous reset is used and the EBR GSR input is disabled. For more information about on-chip memory, see TN1094, On-Chip Memory Usage Guide for LatticeSC Devices. Programmable I/O Cells (PIC) Each PIC contains four PIOs connected to their respective PURESPEED I/O Buffer which are then connected to the PADs as shown in Figure 2-17 ...
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... Register Block DI Input Register Block (including delay and AIL elements*) CEO GSR Update Block POS Update NEG Update PIO B PIO C PIO D 2-16 Architecture LatticeSC/M Family Data Sheet TO PADA "T" DO PURESPEED I/O Buffer DI PADB “C” PADC “T” PADD “C” ...
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... Lattice Semiconductor high-speed interfaces in the LatticeSC devices. Figure 2-18 shows how differential receivers and drivers are arranged between PIOs. Figure 2-18. Differential Drivers and Receivers *Differential Driver only available on right and left of the device. PIO The PIO contains five blocks: an input register block, output register block, tristate register block, update block, and a control logic block ...
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... The AIL operates on single data and double data rate interfaces and is available on most FPGA input pins on the LatticeSC device and all buffer types. The AIL block is low power using only 0.003 mW/MHz typical ( Gbps) for PRBS 2 data ...
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... DDR + shift x1 Adaptive • DDR + shift x2 Input 3 • DDR + shift x4 2 Logic • Shift x1 • Shift x2 3 • Shift x4 2-19 Architecture LatticeSC/M Family Data Sheet INDD INCK INFF To Routing IPOS0 IPOS1 INEG0 INEG1 LCLKIN (ECLK/SCLK) HCLKIN (ECLK/SCLK) LOCK RUNAIL DCNTL[0:8] ...
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... FPGA fabric be output as a higher speed serial stream. Each PIO supports DDR and x2 shift functions. If desired PIOs A and and D can be combined to form x4 shift functions. Figure 2-22 shows a simplified block diagram of the shift register block. LatticeSC/M Family Data Sheet To paired PIO for wide muxing ...
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... Shift x4 From paired PIO Bypass Used for ( x4 shift modes) DDR/DDRX Modes From paired PIO Bypass Used for ( x4 shift modes) DDR/DDRX Modes 2-21 Architecture LatticeSC/M Family Data Sheet To Tri-state Block SDR Register DO (to PURESPEED I/O Buffer) To paired PIO (x4 shift modes) Shift ...
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... When using gearing, any PIO which is not used for gearing can still be used as an output. 1 VCC GND 2 DDR/Shift Register Block DDR • • DDR + half clock 2-22 Architecture LatticeSC/M Family Data Sheet TO (To PURESPEED I/O Buffer) From Output ...
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... ELSR or the local reset LSR. These signals are optionally inverted by the Control Logic Block and provided to the update block as ELSRUP and LSRUP. The Lattice design tools automatically configure and connect the update block when one of the DDR or shift register primitives is used. ...
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... Each bank can support up to two separate VREF voltages, VREF1 and VREF2 that set the threshold for the refer- enced input buffers. In the LatticeSC devices any I/O pin in a bank can be configured dedicated reference voltage supply pin. Each I/O is individually configurable based on the bank’s supply and reference voltages. ...
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... CCIO7 V REF1[7] V TT7 V REF2[7] GND V CCIO6 V REF1[6] V TT6 V REF2[6] GND Table 2-7. Maximum Number of I/Os Per Bank in LatticeSC Family Device LFSC/M15 Bank1 104 Bank2 28 Bank3 60 Bank4 72 Bank5 72 Bank6 60 Bank7 28 Note: Not all the I/Os of the Banks are available in all the packages The LatticeSC devices contain three types of PURESPEED I/O buffers: 1 ...
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... BLVDS, MLVDS, LVPECL, HyperTransport, differential SSTL and differential HSTL. Tables 12 and 13 show the I/O standards (together with their supply and reference voltages) supported by the LatticeSC devices. The tables also provide the available internal termination schemes. For further information on utilizing the PURESPEED I/O buffer to support a variety of standards please see details of additional technical documentation at the end of this data sheet ...
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... None / Diff: 120, 150, 220, 240/ Diff to V 220, 240 / only not specified for off-chip termination or V CCIO CCIO CCIO 2-27 Architecture LatticeSC/M Family Data Sheet On-chip Termination / 2: 50, 60 60, 75, 120, 210 CCIO 50, 60 60, 75, 120, 210 CCIO CCIO ...
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... N/A N/A N/A N/A N/A N/A 3.3 N/A N/A 2-28 Architecture LatticeSC/M Family Data Sheet On-chip Output Termination None. None None, series: 25, 33, 50, 100 None, series: 25, 33, 50, 100 None, series: 25, 33, 50, 100 None, series: 25, 33, 50, 100 None None None, series: 50 None, series: 25, series + parallel to V ...
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... Programmable Termination Many of the I/O standards supported by the LatticeSC devices require termination at the transmitter, receiver or both. The SC devices provide the capability to implement many kinds of termination on-chip, minimizing stub lengths and hence improving performance. Utilizing this feature also has the benefit of reducing the number of discrete compo- nents required on the circuit board ...
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... VCCIO or GND Zo Zo ON-chip OFF-chip VCCIO ON-chip OFF-chip VCCIO ON-chip OFF-chip VCCIO ON-chip OFF-chip 2-30 Architecture LatticeSC/M Family Data Sheet Lattice On-Chip Solution Zo Zo ON-chip OFF-chip VCCIO or GND Zo Zo ON-chip OFF-chip VCCIO 2Zo Zo 2Zo GND ON-chip OFF-chip VCCIO ON-chip OFF-chip VCCIO ...
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... The DDR II memory and RLDRAMII (in Bidirection Data mode) standards require that the on-chip termination turned on when a pin is an input and off when the pin is an output. The LatticeSC devices contain the required cir- cuitry to support this behavior. For additional detail refer to technical information at the end of the data sheet. ...
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... Lattice Semiconductor Differential Input Termination The LatticeSC device allows two types of differential termination. The first is a single resistor across the differential inputs. The second is a center-tapped system where each input is terminated to the on-chip termination bus V The V bus is DC-coupled through an internal capacitor to ground. ...
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... Lattice Semiconductor this allows for easy integration with the rest of the system. These capabilities make the LatticeSC ideal for many multiple power supply and hot-swap applications. The maximum current during hot socketing is 4mA. See Hot Socketing Specifications in Chapter 3 of this data sheet. ...
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... The LatticeSC devices contain a variety of hardware, such as delay elements, DDR registers and PLLs, to simplify the implementation of Source Synchronous interfaces. Table 2-11 lists Source Synchronous and DDR/QDR stan- dards supported in the LatticeSC. For additional detail refer to technical information at the end of the data sheet. Table 2-11. Source Synchronous Standards Table ...
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... The flexiPCS logic is arranged in quads containing logic for four independent full-duplex data channels. Each device in the LatticeSC family has up to eight quads of flexiPCS logic. The LatticeSC Family Selection Guide table on the first page of this data sheet contains the number of flexiPCS channels present on the chip. Note that in some packages (particularly lower pin count packages), not all channels from all quads on a given device may be bonded to package pins ...
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... For example, modes governing user- defined word alignment and multi-channel alignment can be programmed for non-standard protocol applications. For more information on the functions and use of the flexiPCS, refer to the LatticeSC flexiPCS Data Sheet. System Bus Each LatticeSC device connects the FPGA elements with a standardized bus framework referred System Bus ...
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... Additional details of the MPI are provided below. Microprocessor Interface (MPI) The LatticeSC family devices have a dedicated synchronous MPI function block. The MPI is programmable to oper- ate with PowerPC/PowerQUICC MPC860/MPC8260 series microprocessors. The MPI implements an 8-, 16-, or 32-bit interface with 1-bit, 2-bit, or 4-bit parity to the host processor (PowerPC) that can be used for configuration and read-back of the FPGA as well as for user-defi ...
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... Device Configuration All LatticeSC devices contain three possible ports that can be used for device configuration. The serial port, which supports bit-wide configuration, and the sysCONFIG port that supports both byte-wide and serial configuration. The MPI port supports 8-bit, 16-bit or 32-bit configuration. ...
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... This feature is enabled by Lattice’s ispTRACY. The ispTRACY utility is added into the user design at compile time. For additional detail refer to technical information at the end of the data sheet. ...
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... Lattice Semiconductor Density Shifting The LatticeSC family has been designed to ensure that different density devices in the same package have the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration from lower density parts to higher density parts. In many cases also possible to shift a lower utilization design tar- geted for a high-density device to a lower density device. However, the exact details of the fi ...
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... V CCIO © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... CCIO V = 1.2V 1.2V, CC CCIP2 (MAX) CCAUX set to 1.2V nominal. CCIO 3-2 DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. Typ. Max 3.45 — — — Min. Typ. Max <= V (MAX) — — ±1500 IH — — ...
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... LFSC/M40 LFSC/M80 LFSC/M115 LFSC/M15 LFSC/M25 LFSC/M40 LFSC/M80 LFSC/M115 LFSC/M15 LFSC/M25 LFSC/M40 LFSC/M80 LFSC/M115 . CC and 3-3 DC and Switching Characteristics LatticeSC/M Family Data Sheet and V is detailed in the SERDES section DDOB 25°C 85° Typ. Max. All - 449 678 113 798 1255 159 1178 ...
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... CCIO 3-4 DC and Switching Characteristics LatticeSC/M Family Data Sheet V (V) REF Min. Typ. — — — — — — — — — — — — — ...
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... VREF + 0.1 2.65 VREF + 0.1 2.65 VREF + 0.1 2.65 VREF + 0.1 2.65 VREF + 0.1 2.65 VREF + 0.1 2.65 VREF + 0.2 N/A 3-5 DC and Switching Characteristics LatticeSC/M Family Data Sheet Max. V Min (V) (V) (mA) 0.4 2.4 24, 16, 8 0.2 VCCIO - 0.2 0.1 0.4 2 ...
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... CM Over Recommended Operating Conditions Description Min. 500 magnitude -15 560 magnitude -15 500 -15 500 magnitude -15 is 600 mV. CM 3-6 DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. Typ. Max. 0 — 2.4 +/-100 — — 0.05 1.2 2.35 — — +/-10 — 1.38 1.60 0.9V 1.03 — ...
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... |/ between H and L , between H and INP INM + V |/2 0.3+(V INP INM Over Recommended Operating Conditions Description = 100 ohms T 3-7 DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. Typ. Max 100 150 300 — 600 1 1.2 1.4 — — 50 — — 50 200 — ...
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... I and class II) are supported in this mode. MLVDS The LatticeSC devices support the MLVDS standard. This industry standard is emulated using controlled imped- ance complementary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. MLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-1 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor BLVDS The LatticeSC devices support BLVDS standard. This standard is emulated using controlled impedance comple- mentary LVCMOS outputs in conjunction with a parallel external resistor across the driver outputs. BLVDS is intended for use when multi-drop and bi-directional multi-point differential signaling is required. The scheme shown in Figure 3-2 is one possible solution for bi-directional multi-point differential signals ...
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... Lattice Semiconductor LVPECL The LatticeSC devices support differential LVPECL standard. This standard is emulated using controlled imped- ance complementary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The scheme shown in Figure 3-3 is one possible solution for point-to-point signals. Figure 3-3. Differential LVPECL 3 ...
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... True DP RAM Width Cascading (1024x72) DSP Functions 9x9 1-stage Multiplier 18x18 1-Stage Multiplier 9x9 3-Stage Pipelined Multiplier 18x18 4-Stage Pipelined Multiplier 9x9 Constant Multiplier *Typical performance per function DC and Switching Characteristics LatticeSC/M Family Data Sheet Function Function 3-11 -7* Units 6. ...
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... All devices are 100% functionally tested. Listed below are representative values of internal and external timing parameters. For more specific, more precise, and worst-case guaranteed data at a particular temperature and volt- age, use the values reported by the static timing analyzer in the ispLEVER design tool from Lattice and back-anno- tate to the simulation net list. ...
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... No PLL delay tuning (clock injection removal mode, system clock feedback). 2. Using LVCMOS25 12mA I/O. Timing adders for other supported I/O technologies are specified in the LatticeSC Family Timing Adders table. 3. Complete Timing Parameters for a user design are incorporated when running ispLEVER. This is a sampling of the key timing parameters. ...
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... LVCMOS18 LVCMOS 1.8 LVCMOS15 LVCMOS 1.5 LVCMOS12 LVCMOS 1.2 PCI33 PCI PCIX33 PCI-X 3.3 PCIX15 PCI-X 1.5 AGP1X33 AGP-1X 3.3 DC and Switching Characteristics LatticeSC/M Family Data Sheet -7 -6 Min. Max. Min. Max. -0.031 -0.031 -0.011 -0.011 -0.031 -0.031 -0.011 -0.011 -0.031 -0 ...
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... Lattice Semiconductor LatticeSC/M Family Timing Adders (Continued) Over Recommended Operating Conditions at VCC = 1.2V +/- 5% Buffer Type Description AGP2X33 AGP-2X GTLPLUS15 GTLPLUS15 GTL12 GTL12 Output Adjusters LVDS LVDS RSDS RSDS BLVDS25 BLVDS MLVDS25 MLVDS LVPECL33 LVPECL HYPT Hypertransport HSTL18_I HSTL_18 class I HSTL18_II HSTL_18 class II ...
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... Lattice Semiconductor LatticeSC/M Family Timing Adders (Continued) Over Recommended Operating Conditions at VCC = 1.2V +/- 5% Buffer Type Description LVCMOS18_4mA LVCMOS 1.8 4mA drive LVCMOS18_8mA LVCMOS 1.8 8mA drive LVCMOS18_12mA LVCMOS 1.8 12mA drive LVCMOS18_16mA LVCMOS 1.8 16mA drive LVCMOS18_OD LVCMOS 1.8 open drain LVCMOS15_4mA LVCMOS 1 ...
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... LatticeSC/M Family Data Sheet -6 -5 Min. Max. Min. Max. — 0.050 — 0.054 — 0.172 — 0.192 — 0.426 — 0.474 — ...
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... LatticeSC/M Family Data Sheet -6 -5 Min. Max. Min. Max. — 2.116 — 2.335 — 0.444 — 0.498 — — -0.192 — -0.210 — ...
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... HCLK. Note: There is no minimum frequency. If HCLK is sourced from the embedded oscillator, the minimum frequency limitation of the oscillator/ divider is about 0.3 MHz. Refer to the osciallator data for missing configuration modes. DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. 35 1120 ...
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... Rising Edge for latching WREN, WAD and DATAIN. • WREN must continue past falling edge clock. • Data output occurs on negative edge. Figure 3-5. Slice Single/Dual Port Read Cycle Timing WRE CK WRE Old Data Old Data 3-20 DC and Switching Characteristics LatticeSC/M Family Data Sheet ...
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... Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock. Figure 3-7. Read Mode with Input Registers Only CLKA CSA WEA A0 ADA DIA DOA ACCESS ACCESS ACCESS Invalid Data ACCESS Invalid Data output is only updated during a read cycle 3-21 DC and Switching Characteristics LatticeSC/M Family Data Sheet ACCESS ACCESS ACCESS D0 D1 ...
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... Note: Input data and address are registered at the positive edge of the clock and output data appears after the positive of the clock Mem(n) data from previous read DOA Mem(n) data from previous read output is only updated during a read cycle Three consecutive writes ACCESS ACCESS ACCESS D0 D1 3-22 DC and Switching Characteristics LatticeSC/M Family Data Sheet ACCESS ACCESS ACCESS ...
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... RSH t t RSF ACCESS_E t t RSU RSH t ACCESS_F before the Positive FIFO reset edge and enabled t 3-23 DC and Switching Characteristics LatticeSC/M Family Data Sheet ), RW ), RESET hold time (t ) RSF RSH after the FIFO reset negative edge. RSH ), RESET to Flag valid ( RSF ) after the FIFO reset negative edge. ...
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... Figure 3-13. Waveform First Write after Empty Flag CS RCLK RE EF (flag) WCLK WE DC and Switching Characteristics Last Write (FIFO FULL SU1 H1 t SKEW Last Read (FIFO Empty SU1 H1 t SKEW t CO 3-24 LatticeSC/M Family Data Sheet SU1 H1 First Read SU1 First Write ...
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... Over Recommended Operating Conditions Conditions Default duty cycle selected (at 50% levels) 2 MHz ≤ f ≤ 10 MHz PFD f > 10 MHz PFD At 80% level At 20% level 3-25 DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. Typ Max. 2 — 1000 1.5625 — 1000 100 — 1000 2 — ...
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... Output Clock Duty Cycle (at 50% levels, arbitrary duty cycle input clock, duty cycle correction turned on, clock injection removal mode) Applies to all operating conditions At 80% level At 20% level 3-26 DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. Typ. Max. 100 — 700 100 — ...
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... RCLK Low Time (Non-compressed Bitstream) t CLMP RCLK Low Time (Compressed Bitstream) t RCLK High Time CHMP t CCLK to DOUT DMP Over Recommended Operating Conditions Description 3-27 DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. Max. 0 — 600 — 50 (or 100 at — 0.95V) 50 (or 100 at — 0.95V) — ...
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... Lattice Semiconductor LatticeSC/M sysCONFIG Port Timing (Continued) Parameter sysCONFIG Asynchronous Peripheral Configuration Mode t WRN, CS0N and CS1 Pulse Width WRAP t D[7:0] Setup Time SAP t RDY Delay RDYAP t RDY Low BAP t Earliest WRN After RDY Goes High WR2AP RDN to D[7:0] Enable/Disable ...
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... Over Recommended Operating Conditions Parameter t t BTS BTH t BTCPL t t BTCO BTCOEN BTCRH t BTCRS Data Captured t BTUPOEN 3-29 DC and Switching Characteristics LatticeSC/M Family Data Sheet Min. Max. — — 50 — — 10 — — 10 — 20 — 20 — — — 10 — — 25 — 25 — 25 ...
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... Note: Output test conditions for all other interfaces are determined by the respective standards. DUT Test Poi LVCMOS 3.3 = 1.5V LVCMOS 2 30pF LVCMOS 1 LVCMOS 1 LVCMOS 1 CCIO V CCIO 30pF 3-30 DC and Switching Characteristics LatticeSC/M Family Data Sheet Timing Ref — /2 — CCIO /2 — CCIO /2 — CCIO /2 — CCIO / ...
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... VCCJ PROBE_VCC © 2008 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Configuration Pads (Dedicated pins. Used during sysCONFIG.) M[3:0] INITN PROGRAMN DONE CCLK LatticeSC/M Family Data Sheet I/O GND signal - Connected to internal VSS node. Can be used for feed- — back to control an external board power converter. Can be uncon- nected if not used. PLL feedback input. Pull-ups are enabled on input pins during configu- ration ...
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... RDN WRN CS0N CS1 A[21:0] LatticeSC/M Family Data Sheet I/O Reset. (Also sent to general routing). During configuration it resets the configuration state machine. After configuration this pin can perform the global set/reset (GSR) functions or can be used as a general input pin ...
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... MPI_CLK MPI_TSIZ[1:0] MPI_WR_N MPI_BURST MPI_BDIP LatticeSC/M Family Data Sheet I/O In parallel configuration modes, D[7:0] receives configuration data, and each pin is pull-up enabled. For slave serial mode the data input. D[7:3] is the output internal status for peripheral mode when RDN is low ...
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... LatticeSC/M Family Data Sheet I/O Driven active low indicates the start of a transaction on the PowerPC I bus. MPI will strobe the address bus at next rising edge of clock. Address bus driven by a PowerPC bus master. Only 18-bit width is I needed. It has to be the least signifi ...
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... The ispLEVER software tools may specify VDDRX, VDDTX, VDDP and VCCL pins. These pins should be considered VCC12 pins. Note: Signals listed as Signal A / Signal B define the same physical pin that is used for different functions based on configuration mode. LatticeSC/M Family Data Sheet I/O Calibration resistor to be placed between this pin and either ground or RESPN_[ULC/URC] ...
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... Single Ended User / Bank 4 Differential I/O per Bank Bank 5 Bank 6 Bank 7 Bank 2 Bank 3 LVDS Output Pairs Per Bank Bank 6 Bank 7 VCCJ SERDES (signal + power supply) Total LatticeSC/M Family Data Sheet 256 fpBGA 900 fpBGA LFSC/M15 LFSC/M15 LFSC/M25 139 300 378 60 141 182 22 44 ...
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... Differential I/O per Bank Bank 5 Bank 6 Bank 7 Bank 2 Bank 3 LVDS Output Pairs Per Bank Bank 6 Bank 7 VCCJ SERDES (signal + power supply) Total LatticeSC/M Family Data Sheet 1152 fcBGA LFSC/M40 LFSC/M80 LFSC/M115 LFSC/M80 LFSC/M115 604 660 660 302 330 330 78 102 102 ...
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... PL28C 6 PL28D 6 PL31C 6 PL35A 6 PL35B 6 PL35D 6 PL37A 6 PL37B 6 PL41D 6 PL43A 6 4-9 Pinout Information LatticeSC/M Family Data Sheet 1,2 Dual Function ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D VREF2_7 VREF1_7 DIFFR_7 PCLKT7_1 PCLKC7_1 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 PCLKT6_2 PCLKC6_2 VREF1_6 DIFFR_6 ...
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... PB31B 4 PB32A 4 PB32B 4 PB35A 4 PB35B 4 PB36A 4 PB36B 4 PB37A 4 PB37B 4 PB37C 4 4-10 Pinout Information LatticeSC/M Family Data Sheet 1,2 (Cont.) Dual Function LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D VREF1_5 PCLKT5_3 PCLKC5_3 PCLKT5_0 PCLKC5_0 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_2 PCLKC5_2 PCLKT4_2 PCLKC4_2 PCLKT4_1 PCLKC4_1 ...
Page 85
... PR24B 2 PR24A 2 PR23B 2 PR23A 2 PR22D 2 PR22C 2 PR22B 2 PR22A 2 PR18D 2 PR17B 2 4-11 Pinout Information LatticeSC/M Family Data Sheet 1,2 (Cont.) Dual Function PCLKT4_3 PCLKC4_3 VREF1_4 LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E VREF2_3 DIFFR_3 VREF1_3 PCLKC3_2 PCLKT3_2 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 ...
Page 86
... PT33B 1 PT33A 1 PT32D 1 PT32B 1 PT28C 1 PT27B 1 PT27A 1 PT21C 4-12 Pinout Information LatticeSC/M Family Data Sheet 1,2 (Cont.) Dual Function URC_DLLT_IN_C/URC_DLLT_FB_D URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B TDO HDC/SI LDCN/SCS CS1 CS0N RDN WRN QOUT/CEON VREF2_1 DOUT BUSYN/RCLK/SCK PCLKC1_0 PCLKT1_0 VREF1_1 PCS 360 PCS 360 PCS 360 CH 3 OUT P ...
Page 87
... VCC - VCC - VCC - VCC - VCC - VCC - 4-13 Pinout Information LatticeSC/M Family Data Sheet 1,2 (Cont.) Dual Function PCS 360 PCS 360 PCS 360 CH 1 OUT P PCS 360 CH 1 OUT N PCS 360 CH 0 OUT N PCS 360 CH 0 OUT P PCS 360 PCS 360 ...
Page 88
... VCCIO5 P7 VCCIO5 R4 VCCIO5 K2 VCCIO6 N3 VCCIO6 F4 VCCIO7 G3 VCCIO7 Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). 2. The LatticeSC/M15 in a 256-pin package does not support an MPI interface. LFSC/M15 VCCIO Bank VCC - VCC - VCC12 - VCC12 - VCC12 - VCC12 - VCC12 - VCC12 ...
Page 89
... PL25A PL25B VREF1_7 PL25C DIFFR_7 PL25D PCLKT7_1 PL26A PCLKC7_1 PL26B PCLKT7_0 PL27A PCLKC7_0 PL27B PCLKT7_2 PL27C PCLKC7_2 PL27D PCLKT6_0 PL29A PCLKC6_0 PL29B PCLKT6_1 PL29C PCLKC6_1 PL29D 4-15 Pinout Information LatticeSC/M Family Data Sheet 1, 2 LFSC/M25 VCCIO Bank Dual Function - - - - - - - ULC_PLLT_IN_A/ULC_PLLT_FB_B 7 ULC_PLLC_IN_A/ULC_PLLC_FB_B ...
Page 90
... PL48B PL49A PL49B PL51A PL51B VREF2_6 PL51D PL52A PL52B PL55A PL55B PL55C PL55D PL57A PL57B PL57C PL57D XRES VCC12 TEMP VCC12 PB3A PB3B 4-16 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function PCLKT6_3 PCLKT6_2 6 PCLKC6_2 VREF1_6 ...
Page 91
... VREF2_5 PB23D PCLKT5_1 PB24A PCLKC5_1 PB24B PCLKT5_2 PB25A PCLKC5_2 PB25B PB28A PB28B PB29A PB29B PB31A PB31B PB31C PB31D PB32A PB32B PB33A PB33B 4-17 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function 5 LLC_DLLT_IN_C/LLC_DLLT_FB_D 5 LLC_DLLC_IN_C/LLC_DLLC_FB_D 5 LLC_DLLT_IN_D/LLC_DLLT_FB_C 5 LLC_DLLC_IN_D/LLC_DLLC_FB_C VREF1_5 ...
Page 92
... PB51C PCLKT4_3 PB52A PCLKC4_3 PB52B PCLKT4_4 PB52C PCLKC4_4 PB52D PB53A PB53B PB55A PB55B PB56A PB56B PB56C PB60A PB60B PB60C PB67A PB67B VREF1_4 PB67C PB67D PB68A 4-18 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function PCLKT4_2 4 PCLKC4_2 ...
Page 93
... PR44B PR44A PR43B PR43A DIFFR_3 PR42D PR42B PR42A PR38B PR38A PR35B PR35A PR34D VREF1_3 PR34C PR34B PR34A PCLKC3_2 PR31D PCLKT3_2 PR31C 4-19 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function 4 LRC_DLLC_IN_C/LRC_DLLC_FB_D LRC_PLLT_IN_A/LRC_PLLT_FB_B 4 LRC_PLLC_IN_A/LRC_PLLC_FB_B 4 LRC_DLLT_IN_D/LRC_DLLT_FB_C 4 LRC_DLLC_IN_D/LRC_DLLC_FB_C - - - - ...
Page 94
... PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A VCCJ TDO TDO TMS TCK TDI PROGRAMN CFGIRQN/MPI_IRQ_N MPIIRQN CCLK VCC12 VCC12 4-20 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function PCLKT3_3 PCLKC3_1 3 PCLKT3_1 3 PCLKC3_0 3 PCLKT3_0 2 PCLKC2_2 ...
Page 95
... A_HDINP3_R VCC12 A_VDDIB3_R HDC/SI PT49D LDCN/SCS PT49C D8/MPI_DATA8 PT49B CS1/MPI_CS1 PT49A D9/MPI_DATA9 PT47D D10/MPI_DATA10 PT47C CS0N/MPI_CS0N PT47B RDN/MPI_STRB_N PT47A 4-21 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - PCS 3E0 PCS 3E0 PCS 3E0 CH 0 OUT P ...
Page 96
... A9/MPI_ADDR23 PT29B A10/MPI_ADDR24 PT29A A11/MPI_ADDR25 PT28B A12/MPI_ADDR26 PT28A D11/MPI_DATA11 PT27D D12/MPI_DATA12 PT27C A13/MPI_ADDR27 PT27B A14/MPI_ADDR28 PT27A A16/MPI_ADDR30 PT25D D13/MPI_DATA13 PT25C 4-22 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function 1 WRN/MPI_WR_N 1 D7/MPI_DATA7 1 D6/MPI_DATA6 1 D5/MPI_DATA5 1 D4/MPI_DATA4 1 D3/MPI_DATA3 1 D2/MPI_DATA2 1 ...
Page 97
... PCS 360 CH 0 OUT N A_HDOUTN0_L A_VDDOB0_L PCS 360 CH 0 OUT P A_HDOUTP0_L VCC12 PCS 360 A_HDINN0_L PCS 360 A_HDINP0_L A_VDDIB0_L VCC12 PL21A PL21B PL20A 4-23 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function 1 A15/MPI_ADDR29 1 A17/MPI_ADDR31 1 A19/MPI_TSIZ1 1 A20/MPI_BDIP 1 A18/MPI_TSIZ0 ...
Page 98
... PL43D PL47A PL47B PL47D PL47C NC PL53A PL53B PL56A PL56B PB7A PB7B PB8A PB8B PB9A PB9B PB15A PB15D PB23C PB15B PB17A PB17B PB21D PB19A PB19B PB15C PB38D PB49D 4-24 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function ...
Page 99
... PB64B PB65A PB65B PR56B PR56A PR53B PR53A NC NC PR47C PR47D PR47A PR47B PR43D PR43C PR42C PR40B PR40A PR39B PR39A PR36B PR36A PR35C PR48C PR21B PR21A PR20B PR20A 4-25 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function ...
Page 100
... VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 4-26 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 101
... VCC VCC VCC VCC VCC VCC VCC VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX 4-27 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 102
... VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO1 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 VCCIO2 4-28 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 103
... VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO5 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO6 4-29 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 104
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4-30 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 105
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4-31 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 106
... GND GND GND GND GND GND GND GND VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO6 VCCIO6 VCCIO6 VCCIO6 VCCIO5 VCCIO5 4-32 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 107
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4-33 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 108
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC VCC VCC NC RESPN_ULC RESPN_URC 4-34 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M25 VCCIO Bank Dual Function - - - - - - - - - - - - - - - - - ...
Page 109
... VCCIO Number Ball Function Bank B29 Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). 2. The LatticeSC/M15 and LatticeSC/M25 in a 900-pin package supports a 16-bit MPI interface. Dual Function Ball Function NC 4-35 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont ...
Page 110
... ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C VREF2_7 VREF1_7 DIFFR_7 PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 4-36 Pinout Information LatticeSC/M Family Data Sheet 1, 2 LFSC/M40 VCCIO Bank Dual Function - - VCC12 - - RESETN 1 TSALLN 1 DONE 1 INITN ...
Page 111
... PL47C 6 AC27 PL47D 6 AD31 PL48A 6 AC31 PL48B 6 LFSC/M25 Dual Function Ball Function PCLKT6_3 PCLKC6_3 PCLKT6_2 PCLKC6_2 VREF1_6 DIFFR_6 4-37 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PL39A 6 PL39B 6 PL39C 6 PCLKT6_3 PL39D 6 PCLKC6_3 PL40A 6 PL40B 6 PL40C 6 ...
Page 112
... LFSC/M25 Dual Function Ball Function VREF2_6 LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_PLLT_IN_A/LLC_PLLT_FB_B LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C VREF1_5 4-38 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PL61C 6 PL61D 6 PL62A 6 PL62B 6 PL62C 6 PL62D 6 PL65A 6 PL65B ...
Page 113
... Ball Function PCLKT5_3 PCLKC5_3 PCLKT5_4 PCLKC5_4 PCLKT5_5 PCLKC5_5 PCLKT5_0 PCLKC5_0 VREF2_5 PCLKT5_1 PCLKC5_1 PCLKT5_6 PCLKC5_6 PCLKT5_2 PCLKC5_2 PCLKT5_7 PCLKC5_7 4-39 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PB9A 5 PB9B 5 PB11A 5 PB11B 5 PB11C 5 PB11D 5 PB13A 5 PB13B ...
Page 114
... PB46C 4 AG13 PB46D 4 AM11 PB47A 4 AM10 PB47B 4 LFSC/M25 Dual Function Ball Function PCLKT4_2 PCLKC4_2 PCLKT4_7 PCLKC4_7 PCLKT4_1 PCLKC4_1 4-40 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PB38A 5 PB38B 5 PB38C 5 PB38D 5 PB39A 5 PB39B 5 PB39C 5 PB39D 5 PB41A ...
Page 115
... Dual Function Ball Function PCLKT4_6 PCLKC4_6 PCLKT4_0 PCLKC4_0 VREF2_4 PCLKT4_5 PCLKC4_5 PCLKT4_3 PCLKC4_3 PCLKT4_4 PCLKC4_4 VREF1_4 LRC_DLLT_IN_C/LRC_DLLT_FB_D LRC_DLLC_IN_C/LRC_DLLC_FB_D 4-41 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PB54C 4 PCLKT4_6 PB54D 4 PCLKC4_6 PB55A 4 PCLKT4_0 PB55B 4 PCLKC4_0 PB55C ...
Page 116
... PR43A 3 LFSC/M25 Dual Function Ball Function LRC_PLLT_IN_A/LRC_PLLT_FB_B LRC_PLLC_IN_A/LRC_PLLC_FB_B LRC_DLLT_IN_D/LRC_DLLT_FB_C LRC_DLLC_IN_D/LRC_DLLC_FB_C PROBE_VCC PROBE_GND LRC_PLLC_IN_B/LRC_PLLC_FB_A LRC_PLLT_IN_B/LRC_PLLT_FB_A LRC_DLLC_IN_F/LRC_DLLC_FB_E LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_DLLC_IN_E/LRC_DLLC_FB_F LRC_DLLT_IN_E/LRC_DLLT_FB_F VREF2_3 4-42 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PB85A 4 LRC_PLLT_IN_A/LRC_PLLT_FB_B PB85B 4 LRC_PLLC_IN_A/LRC_PLLC_FB_B PB85C 4 LRC_DLLT_IN_D/LRC_DLLT_FB_C PB85D 4 LRC_DLLC_IN_D/LRC_DLLC_FB_C - - ...
Page 117
... VREF1_3 PCLKC3_2 PCLKT3_2 PCLKC3_3 PCLKT3_3 PCLKC3_1 PCLKT3_1 PCLKC3_0 PCLKT3_0 PCLKC2_2 PCLKT2_2 PCLKC2_0 PCLKT2_0 PCLKC2_3 PCLKT2_3 PCLKC2_1 PCLKT2_1 DIFFR_2 VREF1_2 4-43 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PR51D 3 DIFFR_3 PR51C 3 PR51B 3 PR51A 3 PR49D 3 PR49C 3 PR49B 3 ...
Page 118
... A_VDDOB1_R PCS 3E0 CH 1 OUT N A_HDOUTN1_R PCS 3E0 CH 1 OUT P A_HDOUTP1_R PCS 3E0 A_HDINN1_R PCS 3E0 A_HDINP1_R A_VDDIB1_R A_VDDIB2_R PCS 3E0 A_HDINP2_R 4-44 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PR23B 2 PR23A 2 PR25D 2 PR25C 2 PR25B ...
Page 119
... HDC/SI LDCN/SCS D8/MPI_DATA8 CS1/MPI_CS1 D9/MPI_DATA9 D10/MPI_DATA10 CS0N/MPI_CS0N RDN/MPI_STRB_N WRN/MPI_WR_N D7/MPI_DATA7 D6/MPI_DATA6 D5/MPI_DATA5 D4/MPI_DATA4 4-45 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function - PCS 3E0 PCS 3E0 CH 2 OUT PCS 3E0 CH 2 OUT PCS 3E0 CH 3 OUT N ...
Page 120
... VREF1_1 A7/MPI_ADDR21 A8/MPI_ADDR22 A9/MPI_ADDR23 A10/MPI_ADDR24 A11/MPI_ADDR25 A12/MPI_ADDR26 D11/MPI_DATA11 D12/MPI_DATA12 A13/MPI_ADDR27 A14/MPI_ADDR28 A16/MPI_ADDR30 D13/MPI_DATA13 A15/MPI_ADDR29 A17/MPI_ADDR31 A19/MPI_TSIZ1 A20/MPI_BDIP A18/MPI_TSIZ0 4-46 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PT54C 1 D3/MPI_DATA3 PT53B 1 D2/MPI_DATA2 PT53A 1 D1/MPI_DATA1 PT51B 1 D0/MPI_DATA0 PT51A 1 ...
Page 121
... PCS 360 A_HDINP2_L A_VDDIB2_L A_VDDIB1_L PCS 360 A_HDINP1_L PCS 360 A_HDINN1_L PCS 360 CH 1 OUT P A_HDOUTP1_L PCS 360 CH 1 OUT N A_HDOUTN1_L A_VDDOB1_L 4-47 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PT30A 1 MPI_TEA PT28D 1 D14/MPI_DATA14 PT28C 1 DP1/MPI_PAR1 ...
Page 122
... PCS 360 CH 0 OUT N A_HDOUTN0_L A_VDDOB0_L PCS 360 CH 0 OUT P A_HDOUTP0_L PCS 360 A_HDINN0_L PCS 360 A_HDINP0_L A_VDDIB0_L 4-48 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function - PCS 360 CH 0 OUT PCS 360 CH 0 OUT P - PCS 360 ...
Page 123
... VCC12 - E29 VCC12 - E27 VCC12 - E26 VCC12 - E25 VCC12 - E24 VCC12 - LFSC/M25 Dual Function Ball Function VDDAX25_R VDDAX25_L 4-49 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function PR58B 3 PR58A 3 PR57D 3 PR57C 3 PR57B 3 PR57A 3 PR56B 3 PR56A 3 PR22D 2 ...
Page 124
... AK23 GND - AK7 GND - AL1 GND - AL32 GND - AM2 GND - AM31 GND - LFSC/M25 Dual Function Ball Function 4-50 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function VCC12 - VCC12 - VCC12 - VCC12 - VCC12 - VCC12 - VCC12 - VCC12 - VCC12 - VCC12 ...
Page 125
... GND - N12 GND - N14 GND - N19 GND - N21 GND - N29 GND - N3 GND - LFSC/M25 Dual Function Ball Function 4-51 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function GND - GND - GND - GND - GND - GND - GND - GND - GND - GND ...
Page 126
... N16 VCC - N17 VCC - N18 VCC - N20 VCC - P14 VCC - P16 VCC - LFSC/M25 Dual Function Ball Function 4-52 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function GND - GND - GND - GND - GND - GND - GND - GND - GND - GND ...
Page 127
... G4 VCCIO2 - J7 VCCIO2 - K3 VCCIO2 - L10 VCCIO2 - M6 VCCIO2 - N4 VCCIO2 - P9 VCCIO2 - R7 VCCIO2 - LFSC/M25 Dual Function Ball Function 4-53 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - ...
Page 128
... VCCIO7 - N30 VCCIO7 - P23 VCCIO7 - R27 VCCIO7 - AA11 VCCAUX - AA12 VCCAUX - LFSC/M25 Dual Function Ball Function VCCAUX VCCAUX 4-54 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function VCCIO3 - VCCIO3 - VCCIO3 - VCCIO3 - VCCIO3 - VCCIO3 - VCCIO3 - VCCIO3 - VCCIO3 - ...
Page 129
... VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX 4-55 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 VCCIO Bank Dual Function - - - - - - - - - - - - - - - - ...
Page 130
... NC - E23 NC - F23 Differential pair grouping within a PIC is A (True) and B (Complement) and C (True) and D (Complement). 2. The LatticeSC/M25 and LatticeSC/M40 in a 1020-pin package support a 16-bit MPI interface. LFSC/M25 Dual Function Ball Function 4-56 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M40 ...
Page 131
... VREF2_7 PL18D PL20A PL20B PL20C PL20D PL21A PL21B PL21C PL21D PL29A PL29B VREF1_7 PL29C DIFFR_7 PL29D PL31A PL31B PL31C PL31D PL33A PL33B PL33C PL33D PL35A 4-57 Pinout Information LatticeSC/M Family Data Sheet 1, 2 LFSC/M80 VCCIO Bank Dual Function - - - - ULC_PLLT_IN_A/ULC_PLLT_FB_B 7 ULC_PLLC_IN_A/ULC_PLLC_FB_B ULC_DLLT_IN_C/ULC_DLLT_FB_D 7 ...
Page 132
... PL50A PCLKC6_0 PL50B PCLKT6_1 PL50C PCLKC6_1 PL50D PL51A PL51B PCLKT6_3 PL51C PCLKC6_3 PL51D PL52A PL52B PCLKT6_2 PL52C PCLKC6_2 PL52D PL55A PL55B VREF1_6 PL55C PL55D PL56A PL56B 4-58 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function PCLKT7_1 ...
Page 133
... PL76B PL76C DIFFR_6 PL76D PL77A PL77B PL77C PL77D PL78A PL78B PL78C PL78D PL80A PL80B PL80C PL80D PL81A PL81B PL81C PL81D PL82A PL82B PL82C PL82D PL84A PL84B PL84C 4-59 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function ...
Page 134
... PL91C PL91D PL93A PL93B PL93C PL93D PL94A PL94B PL94C PL94D PL95A PL95B PL95C PL95D XRES TEMP PB3A PB3B PB3C PB3D PB4A PB4B PB4C PB4D PB5A PB5B 4-60 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function VREF2_6 ...
Page 135
... PB15C PB15D PB17A PB17B PB17C PB17D PB19A PB19B PB19C PB19D PB21A PB21B PB21C PB21D PB24A PB24B PB24C PB24D PB27A PB27B PB27C PB27D PB29A PB29B PB29C 4-61 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function 5 5 VREF1_5 ...
Page 136
... PCLKT5_7 PB53C PCLKC5_7 PB53D PB56A PB56B PB56C PB56D PB57A PB57B PB57C PB57D PB59A PB59B PB59C PB59D PB60A PB60B PB60C PB60D PB61A PB61B 4-62 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function PCLKT5_3 5 PCLKC5_3 5 PCLKT5_4 5 PCLKC5_4 5 PCLKT5_5 ...
Page 137
... PB74A PCLKC4_2 PB74B PCLKT4_7 PB74C PCLKC4_7 PB74D PCLKT4_1 PB75A PCLKC4_1 PB75B PCLKT4_6 PB75C PCLKC4_6 PB75D PCLKT4_0 PB77A PCLKC4_0 PB77B VREF2_4 PB77C PB77D PCLKT4_5 PB79A PCLKC4_5 PB79B PB79C 4-63 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function ...
Page 138
... PB107A PB107B PB107C PB107D PB109A PB109B PB109C PB109D PB111A PB111B PB111C PB111D PB113A PB113B PB113C PB113D PB115A PB115B PB115C PB115D PB117A PB117B 4-64 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function 4 4 PCLKT4_3 4 PCLKC4_3 4 PCLKT4_4 4 PCLKC4_4 ...
Page 139
... PROBE_GND PR95D PR95C PR95B PR95A PR94D PR94C PR94B PR94A PR93D PR93C PR93B PR93A PR91D PR91C PR91B PR91A PR90D PR90C PR90B PR90A VREF2_3 PR89D 4-65 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function VREF1_4 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D 4 LRC_DLLC_IN_C/LRC_DLLC_FB_D ...
Page 140
... PR81D PR81C PR81B PR81A PR80D PR80C PR80B PR80A PR78D PR78C PR78B PR78A PR77D PR77C PR77B PR77A DIFFR_3 PR76D PR76C PR76B PR76A PR65D PR65C PR65B PR65A PR63D PR63C 4-66 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function ...
Page 141
... PCLKT3_0 PR50A PCLKC2_2 PR48D PCLKT2_2 PR48C PCLKC2_0 PR48B PCLKT2_0 PR48A PCLKC2_3 PR47D PCLKT2_3 PR47C PCLKC2_1 PR47B PCLKT2_1 PR47A PR46D PR46C PR46B PR46A PR43D PR43C PR43B 4-67 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function VREF1_3 PCLKC3_2 ...
Page 142
... DIFFR_2 PR29D VREF1_2 PR29C PR29B PR29A PR21D PR21C PR21B PR21A PR20D PR20C PR20B PR20A VREF2_2 PR18D PR18C PR18B PR18A PR17D PR17C PR17B PR17A PR16D PR16C PR16B PR16A 4-68 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function ...
Page 143
... PCS 3E0 CH 2 OUT N A_HDOUTN2_R A_VDDOB3_R PCS 3E0 CH 3 OUT N A_HDOUTN3_R VCC12 PCS 3E0 CH 3 OUT P A_HDOUTP3_R PCS 3E0 A_HDINN3_R PCS 3E0 A_HDINP3_R VCC12 A_VDDIB3_R VCC12 4-69 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - TDO - - - 1 1 CFGIRQN/MPI_IRQ_N 1 ...
Page 144
... PT77A D9/MPI_DATA9 PT75D D10/MPI_DATA10 PT75C CS0N/MPI_CS0N PT75B RDN/MPI_STRB_N PT75A WRN/MPI_WR_N PT74D D7/MPI_DATA7 PT74C D6/MPI_DATA6 PT74B 4-70 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - PCS 3E1 PCS 3E1 PCS 3E1 CH 0 OUT PCS 3E1 CH 0 OUT N ...
Page 145
... PT61B A4/MPI_ADDR18 PT61A D25/PCLKC1_5/MPI_DATA25 PT60D D26/PCLKT1_5/MPI_DATA26 PT60C A5/MPI_ADDR19 PT60B A6/MPI_ADDR20 PT60A D27/MPI_DATA27 PT59D VREF1_1 PT59C A7/MPI_ADDR21 PT59B A8/MPI_ADDR22 PT59A 4-71 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 Ball VCCIO Bank Dual Function 1 D5/MPI_DATA5 1 D4/MPI_DATA4 1 D3/MPI_DATA3 1 D2/MPI_DATA2 1 D1/MPI_DATA1 1 D16/PCLKC1_3/MPI_DATA16 1 D17/PCLKT1_3/MPI_DATA17 ...
Page 146
... PCS 361 CH 2 OUT N B_HDOUTN2_L B_VDDOB2_L PCS 361 CH 2 OUT P B_HDOUTP2_L VCC12 PCS 361 B_HDINN2_L PCS 361 B_HDINP2_L B_VDDIB2_L VCC12 B_VDDIB1_L VCC12 4-72 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 Ball VCCIO Bank Dual Function 1 D28/PCLKC1_6/MPI_DATA28 1 D29/PCLKT1_6/MPI_DATA29 1 A9/MPI_ADDR23 1 A10/MPI_ADDR24 ...
Page 147
... PCS 360 CH 0 OUT N A_HDOUTN0_L A_VDDOB0_L PCS 360 CH 0 OUT P A_HDOUTP0_L VCC12 PCS 360 A_HDINN0_L PCS 360 A_HDINP0_L A_VDDIB0_L 4-73 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - PCS 361 PCS 361 PCS 361 CH 1 OUT P ...
Page 148
... PL59B PL61A PL61B PL64A PL64B PL67A PL67B PL68A PL68B PL69A PL69B PR69B PR69A PR68B PR68A PR67B PR67A PR64B PR64A PR61B PR61A PR59B PR59A PR41D PR41C PR41B PR41A 4-74 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - ...
Page 149
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4-75 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function ...
Page 150
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4-76 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 151
... GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 4-77 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 152
... VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC 4-78 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 153
... VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX VCCAUX 4-79 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 154
... VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO3 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 VCCIO4 4-80 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 155
... VCCIO6 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO7 VCCIO1 VTT_2 VTT_2 VTT_2 VTT_3 VTT_3 VTT_3 VTT_4 VTT_4 VTT_4 4-81 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M80 VCCIO Bank Dual Function - - - - - - - - - - - - - - - ...
Page 156
... J12 NC - H12 NC - H23 NC - J23 Differential pair grouping within a PCI is A (True) and B (complement) and C (True) and D (Complement). 2. The LatticeSC/M40 and LatticeSC/M80 in an 1152-pin package support a 32-bit MPI interface. Ball Dual Function Function VTT_5 VTT_5 VTT_5 VTT_6 VTT_6 VTT_6 VTT_7 VTT_7 VTT_7 ...
Page 157
... DONE 1 INITN PL15A 7 PL15B PL17A 7 PL17B PL18A 7 PL18B PL19A 7 PL19B PL26A 7 PL26B PL43A 7 PL43B PL45A 7 PL45B PL47A 7 PL47B 7 4-83 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ULC_PLLT_IN_A/ULC_PLLT_FB_B ULC_PLLC_IN_A/ULC_PLLC_FB_B ULC_DLLT_IN_C/ULC_DLLT_FB_D ULC_DLLC_IN_C/ULC_DLLC_FB_D ULC_PLLT_IN_B/ULC_PLLT_FB_A ULC_PLLC_IN_B/ULC_PLLC_FB_A ULC_DLLT_IN_D/ULC_DLLT_FB_C ULC_DLLC_IN_D/ULC_DLLC_FB_C VREF2_7 VREF1_7 DIFFR_7 ...
Page 158
... PL57A 7 PL57B PL60A 7 PL60B PL61A 7 PL61B PL62A 7 PL62B PL64A 6 PL64B PL65A 6 PL65B PL66A 6 PL66B PL69A 6 4-84 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function PCLKT7_1 PCLKC7_1 PCLKT7_3 PCLKC7_3 PCLKT7_0 PCLKC7_0 PCLKT7_2 PCLKC7_2 PCLKT6_0 PCLKC6_0 PCLKT6_1 PCLKC6_1 PCLKT6_3 PCLKC6_3 PCLKT6_2 PCLKC6_2 ...
Page 159
... AF32 AA25 PL96C AB25 PL96D LFSC/M115 VCCIO Bank PL69B PL70A 6 PL70B PL71A 6 PL71B PL74A 6 PL74B PL77A 6 PL77B PL79A 6 PL79B PL90A 6 PL90B PL91A 6 PL91B PL92A 6 PL92B PL94A 6 PL94B PL96A 6 PL96B 4-85 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function VREF1_6 DIFFR_6 ...
Page 160
... AD25 PL116D AL32 PL117A AL31 PL117B AG29 PL117C AG28 PL117D AF28 AF27 AM33 LFSC/M115 VCCIO Bank PL98A 6 PL98B PL99A 6 PL99B XRES - TEMP 6 PB3A 5 4-86 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function VREF2_6 LLC_DLLT_IN_E/LLC_DLLT_FB_F LLC_DLLC_IN_E/LLC_DLLC_FB_F LLC_DLLT_IN_F/LLC_DLLT_FB_E LLC_DLLC_IN_F/LLC_DLLC_FB_E LLC_PLLT_IN_B/LLC_PLLT_FB_A LLC_PLLC_IN_B/LLC_PLLC_FB_A LLC_PLLT_IN_A/LLC_PLLT_FB_B ...
Page 161
... PB23A AN26 PB23B AF24 PB23C AF23 PB23D LFSC/M115 VCCIO Bank PB3B 5 PB3C 5 PB3D 5 PB4A 5 PB4B 5 PB4C 5 PB4D 5 PB5A 5 PB5B 5 PB5C 5 PB5D 5 PB7A 5 PB7B 5 PB7C 5 PB7D 4-87 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function LLC_PLLC_IN_A/LLC_PLLC_FB_B LLC_DLLT_IN_C/LLC_DLLT_FB_D LLC_DLLC_IN_C/LLC_DLLC_FB_D LLC_DLLT_IN_D/LLC_DLLT_FB_C LLC_DLLC_IN_D/LLC_DLLC_FB_C VREF1_5 ...
Page 162
... PB53A AM22 PB53B AJ24 PB53C AJ23 PB53D AN21 PB54A AN20 PB54B AE19 PB54C AD19 PB54D AK21 PB55A AK20 PB55B AK23 PB55C AK22 PB55D AL20 PB58A AL19 PB58B AG19 PB58C AF19 PB58D AP21 PB61A LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank ...
Page 163
... PB75D AK17 PB78A AK16 PB78B AG17 PB78C AF17 PB78D AM16 PB81A AM15 PB81B AJ15 PB81C AJ14 PB81D AL16 PB83A AL15 PB83B AG16 PB83C AF16 PB83D AP15 PB86A AP14 PB86B AH15 PB86C AH14 PB86D LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank ...
Page 164
... PB113A AN10 PB113B AF14 PB113C AF13 PB113D AM10 PB115A AM9 PB115B AE14 PB115C AE13 PB115D AP9 PB118A AP8 PB118B AK11 PB118C AK10 PB118D AL10 PB121A AL9 PB121B AF12 PB121C AF11 PB121D AN9 PB123A LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank ...
Page 165
... PB135D AN5 PB138A AN4 PB138B AH9 PB138C AH8 PB138D AM3 PB139A AM4 PB139B AG9 PB139C AG8 PB139D AN2 PB141A AM2 PB141B AJ6 PB141C AH6 PB141D AF7 PROBE_VCC AF8 PROBE_GND AG7 PR117D AG6 PR117C LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank ...
Page 166
... PR103B AE4 PR103A AD6 PR99D AC6 PR99C AG2 PR99B AF2 PR99A AC8 PR98D AB8 PR98C AK1 PR98B AJ1 PR98A AB10 PR96D AA10 PR96C AF3 PR96B AE3 PR96A AE5 PR94D LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank 3 LRC_DLLC_IN_F/LRC_DLLC_FB_E 3 LRC_DLLT_IN_F/LRC_DLLT_FB_E LRC_DLLC_IN_E/LRC_DLLC_FB_F 3 LRC_DLLT_IN_E/LRC_DLLT_FB_F ...
Page 167
... PR79A AA6 PR77D Y6 PR77C Y4 PR77B W4 PR77A W11 PR74D V11 PR74C W2 PR74B V2 PR74A W9 PR71D V9 PR71C V1 PR71B U1 PR71A W10 PR70D V10 PR70C U2 PR70B T2 PR70A Y8 PR69D W8 PR69C W5 PR69B V5 PR69A V7 PR66D U7 PR66C T1 PR66B R1 PR66A LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank 4-93 Pinout Information ...
Page 168
... PR60B N1 PR60A R6 PR57D P6 PR57C M1 PR57B L1 PR57A T10 PR56D U10 PR56C N2 PR56B M2 PR56A R11 PR51D P11 PR51C N4 PR51B M4 PR51A N5 PR49D M5 PR49C L2 PR49B K2 PR49A P8 PR47D N8 PR47C J2 PR47B H2 PR47A M6 PR45D L6 PR45C K3 PR45B LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank 4-94 Pinout Information Dual Function ...
Page 169
... LFSC/M115 VCCIO Bank VCCJ - TDO - TMS - TCK - TDI - 1 1 CCLK 4-95 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function DIFFR_2 VREF1_2 VREF2_2 URC_DLLC_IN_D/URC_DLLC_FB_C URC_DLLT_IN_D/URC_DLLT_FB_C URC_PLLC_IN_B/URC_PLLC_FB_A URC_PLLT_IN_B/URC_PLLT_FB_A URC_DLLC_IN_C/URC_DLLC_FB_D URC_DLLT_IN_C/URC_DLLT_FB_D URC_PLLC_IN_A/URC_PLLC_FB_B URC_PLLT_IN_A/URC_PLLT_FB_B TDO CFGIRQN/MPI_IRQ_N PCS 3E0 PCS 3E0 PCS 3E0 CH 0 OUT P ...
Page 170
... D11 B_VDDOB1_R B12 B_HDOUTN1_R L10 VCC12 A12 B_HDOUTP1_R F11 B_HDINN1_R E11 B_HDINP1_R G11 VCC12 D8 B_VDDIB1_R G12 VCC12 LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank - - PCS 3E0 CH 0 OUT PCS 3E0 CH 1 OUT PCS 3E0 CH 1 OUT P - PCS 3E0 PCS 3E0 ...
Page 171
... PT86D H14 PT86C A16 PT86B B16 PT86A J13 PT83D H13 PT83C D15 PT83B E15 PT83A J16 PT81D LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank - - PCS 3E1 PCS 3E1 PCS 3E1 CH 2 OUT PCS 3E1 CH 2 OUT PCS 3E1 CH 3 OUT N ...
Page 172
... PT63A H21 PT61D J21 PT61C A19 PT61B B19 PT61A H22 PT58D J22 PT58C F20 PT58B G20 PT58A K21 PT57D K22 PT57C A20 PT57B B20 PT57A LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank 1 D20/PCLKT1_2/MPI_DATA20 1 MCA_CLK_P1_OUT 1 1 D21/PCLKC1_1/MPI_DATA21 1 D22/PCLKT1_1/MPI_DATA22 1 MCA_CLK_P2_OUT BUSYN/RCLK/SCK PCLKT1_0/MPI_CLK ...
Page 173
... G23 VCC12 D27 B_VDDIB1_L G24 VCC12 E24 B_HDINP1_L F24 B_HDINN1_L A23 B_HDOUTP1_L L25 VCC12 B23 B_HDOUTN1_L D24 B_VDDOB1_L B24 B_HDOUTN0_L D25 B_VDDOB0_L A24 B_HDOUTP0_L K25 VCC12 LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Bank PCS 361 PCS 361 PCS 361 CH 3 OUT P ...
Page 174
... PL34A 7 PL34B 7 PL38A 7 PL38B 7 PL40A 7 4-100 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function PCS 361 PCS 361 PCS 360 PCS 360 PCS 360 CH 3 OUT P PCS 360 CH 3 OUT N PCS 360 CH 2 OUT N PCS 360 CH 2 OUT P PCS 360 ...
Page 175
... PR73A R5 PR55D P5 PR55C K1 PR55B J1 PR55A R7 PR53D P7 PR53C N3 PR53B M3 PR53A H1 PR40B G1 PR40A LFSC/M115 VCCIO Bank PL40B 7 PL53A 7 PL53B PL55A 7 PL55B PL73A 6 PL73B 6 PL75A 6 PL75B 6 PL78A 6 PL78B 6 PL81A 6 PL81B 6 PL82A 6 PL82B 6 PL83A 6 PL83B 4-101 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 176
... GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - 4-102 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 177
... GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - 4-103 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 178
... GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - GND - 4-104 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 179
... VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - VCC - 4-105 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 180
... VCCAUX N12 VCCAUX N16 VCCAUX N17 VCCAUX N18 VCCAUX N19 VCCAUX N23 VCCAUX P12 VCCAUX P23 VCCAUX T13 VCCAUX T22 VCCAUX U12 VCCAUX U13 VCCAUX LFSC/M115 VCCIO Bank VCC - VCC - - - - - - - - - - - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - 4-106 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 181
... VCCIO3 AC10 VCCIO3 AD4 VCCIO3 AE6 VCCIO3 AG3 VCCIO3 AK4 VCCIO3 T7 VCCIO3 U3 VCCIO3 V4 VCCIO3 W6 VCCIO3 Y10 VCCIO3 AD12 VCCIO4 AF15 VCCIO4 AF9 VCCIO4 AH10 VCCIO4 LFSC/M115 VCCIO Bank - - - - - - GND - GND - - - - - - - - - GND - - - - - - - - - - - - - - - - - - - - - - - - - - - 4-107 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 182
... V32 VCCIO6 W28 VCCIO6 Y26 VCCIO6 E31 VCCIO7 G28 VCCIO7 H32 VCCIO7 K29 VCCIO7 L31 VCCIO7 M25 VCCIO7 N28 VCCIO7 P32 VCCIO7 R25 VCCIO7 J25 VCCIO1 N11 LFSC/M115 VCCIO Bank - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - VTT_2 2 4-108 Pinout Information LatticeSC/M Family Data Sheet 1, 2 Dual Function ...
Page 183
... AA13 VCC12 P13 VCC12 N14 VCC12 G26 G9 J12 H12 H23 J23 1. Differential pair grouping within a PCI is A (True) and B (complement) and C (True) and D (Complement). 2. The LatticeSC/M115 in an 1152-pin package supports a 32-bit MPI interface. LFSC/M115 VCCIO Bank VTT_2 2 VTT_2 2 VTT_3 3 VTT_3 3 VTT_3 3 ...
Page 184
... PL18B PL18C VREF2_7 PL18D PL19A PL19B PL19C PL19D PL26A PL26B PL26C PL26D PL30A PL30B PL30C PL30D PL34A PL34B PL34C PL34D PL38A PL38B PL38C PL38D PL40A 4-110 Pinout Information LatticeSC/M Family Data Sheet 1, 2 LFSC/M115 VCCIO Dual Bank Function - - - - ULC_PLLT_IN_A/ULC_PLLT_FB_B 7 ULC_PLLC_IN_A/ULC_PLLC_FB_B ULC_DLLT_IN_C/ULC_DLLT_FB_D ...
Page 185
... PL48B PL48C PL48D PL49A PL49B PL49C PL49D PL51A PL51B PL51C PL51D PL52A PL52B PL52C PL52D PL53A PL53B PL53C PL53D PL55A PL55B PL55C PL55D PL56A PL56B 4-111 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function VREF1_7 7 DIFFR_7 ...
Page 186
... PL65D PL66A PL66B PCLKT6_2 PL66C PCLKC6_2 PL66D PL69A PL69B VREF1_6 PL69C PL69D PL70A PL70B PL70C PL70D PL71A PL71B PL71C PL71D PL73A PL73B PL73C 4-112 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function PCLKT7_1 7 PCLKC7_1 7 PCLKT7_3 7 PCLKC7_3 ...
Page 187
... PL79B PL79C PL79D PL81A PL81B PL81C PL81D PL82A PL82B PL82C PL82D PL83A PL83B PL83C PL83D PL86A PL86B PL86C PL86D PL87A PL87B PL87C PL87D PL88A PL88B PL88C PL88D 4-113 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function ...
Page 188
... PL98A PL98B PL98C PL98D PL99A PL99B PL99C PL99D PL103A PL103B PL103C PL103D PL104A PL104B PL104C PL104D PL107A PL107B PL107C VREF2_6 PL107D PL109A PL109B PL109C PL109D PL112A 4-114 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function DIFFR_6 ...
Page 189
... PB4C PB4D PB5A PB5B PB5C VREF1_5 PB5D PB7A PB7B PB7C PB7D PB9A PB9B PB9C PB9D PB11A PB11B PB11C PB11D PB12A PB12B PB12C PB12D 4-115 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function LLC_DLLT_IN_E/LLC_DLLT_FB_F 6 LLC_DLLC_IN_E/LLC_DLLC_FB_F LLC_DLLT_IN_F/LLC_DLLT_FB_E 6 LLC_DLLC_IN_F/LLC_DLLC_FB_E ...
Page 190
... PB19C PB19D PB20A PB20B PB20C PB20D PB21A PB21B PB21C PB21D PB23A PB23B PB23C PB23D PB25A PB25B PB25C PB25D PB26A PB26B PB26C PB26D PB27A PB27B PB27C PB27D PB29A 4-116 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function ...
Page 191
... PB34D PB35A PB35B PB35C PB35D PB37A PB37B PB37C PB37D PB38A PB38B PB38C PB38D PB39A PB39B PB39C PB39D PB41A PB41B PB41C PB41D PB42A PB42B PB42C PB42D PB43A PB43B 4-117 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function ...
Page 192
... PB53C VREF2_5 PB53D PCLKT5_1 PB54A PCLKC5_1 PB54B PCLKT5_6 PB54C PCLKC5_6 PB54D PCLKT5_2 PB55A PCLKC5_2 PB55B PCLKT5_7 PB55C PCLKC5_7 PB55D PB57A PB57B PB57C PB57D PB58A PB58B PB58C 4-118 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function PCLKT5_3 ...
Page 193
... PB71B PB71C PB71D PB73A PB73B PB73C PB73D PB75A PB75B PB75C PB75D PB78A PB78B PB78C PB78D PB81A PB81B PB81C PB81D PB83A PB83B PB83C PB83D PB86A PB86B PB86C PB86D 4-119 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function ...
Page 194
... PB95A PB95B PB95C PB95D PB97A PB97B PB97C PB97D PB98A PB98B PB98C PB98D PB99A PB99B PB99C PB99D PB101A PB101B PB101C PB101D PB102A 4-120 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function PCLKT4_2 4 PCLKC4_2 4 PCLKT4_7 4 PCLKC4_7 4 PCLKT4_1 4 PCLKC4_1 ...
Page 195
... PB107D PB109A PB109B PB109C PB109D PB110A PB110B PB110C PB110D PB111A PB111B PB111C PB111D PB113A PB113B PB113C PB113D PB114A PB114B PB114C PB114D PB115A PB115B PB115C PB115D PB117A PB117B 4-121 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function ...
Page 196
... PB123A PB123B PB123C PB123D PB125A PB125B PB125C PB125D PB126A PB126B PB126C PB126D PB127A PB127B PB127C PB127D PB129A PB129B PB129C PB129D PB130A PB130B PB130C PB130D PB131A PB131B PB131C 4-122 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function ...
Page 197
... PB139D PB141A PB141B PB141C PB141D PROBE_VCC PROBE_GND PR117D PR117C PR117B PR117A PR116D PR116C PR116B PR116A PR115D PR115C PR115B PR115A PR112D PR112C PR112B PR112A PR109D PR109C 4-123 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function VREF1_4 4 4 LRC_DLLT_IN_C/LRC_DLLT_FB_D ...
Page 198
... PR98B PR98A PR96D PR96C PR96B PR96A PR94D PR94C PR94B PR94A PR92D PR92C PR92B PR92A PR91D PR91C PR91B PR91A DIFFR_3 PR90D PR90C PR90B PR90A PR88D PR88C PR88B 4-124 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function VREF2_3 ...
Page 199
... PR81C PR81B PR81A PR79D PR79C PR79B PR79A PR78D PR78C PR78B PR78A PR77D PR77C PR77B PR77A PR75D PR75C PR75B PR75A PR74D PR74C PR74B PR74A PR73D PR73C PR73B PR73A 4-125 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function ...
Page 200
... PR62B PCLKT2_0 PR62A PCLKC2_3 PR61D PCLKT2_3 PR61C PCLKC2_1 PR61B PCLKT2_1 PR61A PR60D PR60C PR60B PR60A PR57D PR57C PR57B PR57A PR56D PR56C PR56B PR56A PR55D 4-126 Pinout Information LatticeSC/M Family Data Sheet 1, 2 (Cont.) LFSC/M115 VCCIO Dual Bank Function VREF1_3 PCLKC3_2 3 PCLKT3_2 3 ...