HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 6

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

Functional Description
The HSP50210 Digital Costas Loop (DCL) contains most of
the baseband processing functions needed to implement a
digital Costas Loop Demodulator. These functions include
LO generation/mixing, matched filtering, AGC, carrier phase
and frequency error detection, timing error detection, carrier
loop filtering, bit sync loop filtering, lock detection,
acquisition/tracking control, and soft decision slicing for
forward error correction algorithms. While the DCL is
designed to work with the HSP50110 Digital Quadrature
Tuner (DQT) as a variable rate PSK demodulator for satellite
demodulation, functions on the chip are common to many
communications receivers.
The DCL provides the processing blocks for the three
tracking loops commonly found in a data demodulator: the
Automatic Gain Control (AGC) loop, the Carrier Tracking
Loop, and a Symbol Tracking Loop. The AGC loop adjusts
for input signal power variations caused by path loss or
signal-to-noise variations. The carrier tracking loop removes
the frequency and phase uncertainties in the carrier due to
oscillator inaccuracies and doppler. The symbol tracking
loop removes the frequency and phase uncertainties in the
data and generates a recovered clock synchronous with the
received data. Each loop consists of an error detector, a loop
filter, and a frequency or gain adjustment/control. The AGC
loop is internal to the DCL, while the symbol and carrier
tracking loops are closed external to the DCL. When the
DCL is used together with the HSP50110, the tracking loops
are closed around the baseband filtering to center the signal
in the filter bandwidth. In addition, the AGC function is
divided between the two chips with the HSP50110 providing
the coarse AGC, and the HSP50210 providing the fine or
final AGC.
A top level block diagram of the HSP50210 is shown in
Figure 1. This diagram shows the major blocks and the
multiplexers used to reconfigure the data path for various
architectures.
Input Controller
In-Phase (I) and Quadrature (Q) data enters the part through
the Input Controller. The 10-bit data enters in either serial or
parallel fashion using either two’s complement or offset
binary format. The input mode and binary format is set in the
Data Path Configuration Control Register, bits 14 and 15
(see Table 15 on page 32).
If Parallel Input mode is selected, I and Q data are clocked
into the part through IIN0-9 and QIN0-9 respectively. Data
enters the processing pipeline when the input enable
(SYNC) is sampled “low” by the processing clock (CLK). The
enable signal is pipelined with the data to the various
processing elements to minimize pipeline delay where
possible. As a result, the pipeline delay through the AGC,
Carrier Tracking, and Symbol Tracking Loop Filters is
measured in CLKs; not input data samples.
6
HSP50210
If serial input mode is selected, the I and Q data enters via
the ISER and QSER pins using SERCLK and SSYNC. The
beginning of a serial word is designated by asserting
SSYNC ‘high’ one SERCLK prior to the first data bit, as
shown in Figure 2. On the following SERCLKs, data is
shifted into the register until all 10 bits have been input. Data
shifting is then disabled and the contents of the register are
held until the next assertion of SSYNC. The assertion of a
SSYNC transfers data into the processing pipeline, and the
Shift Register is enabled to accept new data on the following
SERCLK. When data is transferred to the processing
pipeline by SSYNC, a processing enable is generated which
follows the data through the pipeline. This enable allows the
delay through processing elements (like the loop filters) to be
minimized since their pipeline delay is expressed in CLKs
not SSYNC periods. Note: SSYNC should not be
asserted for more than one SERCLK cycle.
NOTE: Data must be loaded MSB first.
FIGURE 2. SERIAL INPUT TIMING FOR ISER AND QSER INPUTS
Input Level Detector
The Input Level Detector generates a one-bit error signal for
an external IF AGC filter and amplifier. The error signal is
generated by comparing the magnitude of the input samples
to a user programmable threshold. The HI/LO pin is then
driven “high” or “low” depending on the relationship of its
magnitude to the threshold. The sense of the HI/LO pin is
programmable so that a magnitude exceeding the threshold
can either be represented as a “high” or “low” logic state.
The Input Level Detector (HI/LO output) threshold and the
sense are set by the Data Path Configuration Control
Register bits 16 to 23 and 13 (see Table 15 page 32).
Note: The Input Level Detector is typically not used in
applications which use the HSP50210 with the
HSP50110.
The high/low outputs can be integrated by an external loop
filter to close an AGC loop. Using this method, the gain of
the loop forces the median magnitude of the input samples
to the threshold. When the magnitude of half of the samples
is above the threshold (and half is below), the error signal is
integrated to zero by the loop filter. The magnitude of the
complex input is estimated using Equation 1:
Mag (I, Q)
Mag (I, Q)
ISER/QSER
SERCLK
SSYNC
=
=
I
Q
+
+
0.375
0.375
MSB
SSYNC LEADS 1st DATA BIT
×
×
Q if I
I if Q
>
>
Q and
I
MSB
July 2, 2008
FN3652.5
(EQ. 1)