HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 35

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

POSITION
POSITION
POSITION
POSITION
31-8
31-0
31-0
BIT
BIT
BIT
BIT
4-0
7-6
5
5
4
3
2
1
0
Lead/Lag to Internal
NCO Routing
Error Accumulation
Not Used
Reserved
Lead Phase Error
Enable
Lag Phase Error
Enable
AFC Enable
Carrier Sweep Enable
Invert Carrier Phase
Error
Invert Carrier
Frequency Error
Carrier Loop Filter
Upper limit
Carrier Loop Filter
Lower limit
FUNCTION
FUNCTION
FUNCTION
FUNCTION
35
TABLE 21. CARRIER LOOP FILTER CONTROL REGISTER #1 (Continued)
TABLE 24. CARRIER LOOP FILTER LOWER LIMIT CONTROL REGISTER
TABLE 23. CARRIER LOOP FILTER UPPER LIMIT CONTROL REGISTER
TABLE 22. CARRIER LOOP FILTER CONTROL REGISTER #2
0 = Sum of lead and lag paths routed to the internal NCO. (32 MSBs of sum are routed).
1 = The lead term is routed to the internal NCO. (32 MSBs of lead term are routed).
These bits set the number of phase and frequency error measurements that are accumulated before the
Carrier and AFC Loop Filters are run. Since the Loop Filters can only accept new inputs every 6 CLKs
(normally at the symbol rate), the error accumulation is required to ensure that no phase or frequency
error outputs are missed when error terms are generated at a rate greater than 1/6 CLK (see “Carrier
Phase Error Detector” on page 18). The 5-bit value programmed here should be set to one less than the
desired number of error terms to accumulate. For example, setting these bits to 0011 (BINARY) would
cause 4 error terms to be accumulated. A total range from 1 to 32 is provided.
When error accumulation is used, divide the Lead Gain by the number of errors accumulated. Note that
the LAG Gain does not need to be scaled since it increases to compensate for the delay, since it is an
accumulator.
No programming required.
Reserved. Set to 0 for proper operation.
0 = Carrier Phase Error enabled to lead processing path of loop filter.
1 = Carrier Phase Error to lead processing path of loop filter zeroed.
0 = Carrier Phase Error enabled to lag processing path of loop filter.
1 = Carrier Phase Error to lag processing path of loop filter zeroed (First Order Loop).
0 = Frequency error enabled to lag processing path of Carrier Loop Filter.
1 = Frequency error zeroed.
0 = Frequency sweep input to the lag path of the Carrier Loop Filter enabled.
1 = Sweep input to Carrier Loop Filter zeroed.
0 = Carrier Phase Error is normal into Carrier Loop Filter.
1 = Carrier Phase Error is inverted into Carrier Loop Filter.
0 = Carrier Frequency Error is normal into AFC loop filter.
1 = Carrier Frequency Error is inverted into AFC Loop filter.
The 32-bit two’s complement value programmed here sets the upper sweep and tracking limit of the Carrier
Loop Filter by setting the upper limit of the loop filter’s lag accumulator. If the limit is exceeded, the upper 32
bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
The 32-bit two’s complement value programmed here sets the Lower sweep and tracking limit of the Carrier
Loop Filter by setting the lower limit of the loop filter’s lag accumulator. If the running sum falls below the limit,
the upper 32 bits of the 40-bit accumulator are set to the limit, and the 8 LSBs are set to zero.
DESTINATION ADDRESS = 6
DESTINATION ADDRESS = 7
DESTINATION ADDRESS = 8
DESTINATION ADDRESS = 9
HSP50210
DESCRIPTION
DESCRIPTION
DESCRIPTION
DESCRIPTION
July 2, 2008
FN3652.5