HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 24

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

State Machine (see Figure 16). The function of the Lock
Detector is to monitor the baseband symbols and to decide
whether the Carrier Tracking Loop is locked to the input
signal. Note: The Symbol Tracking Loop locks
independently; under most circumstances, it will lock before
the Carrier Tracking Loop locks up. Based on the
in-lock/out-of-lock decision, either the Acquisition or Tracking
parameters are selected in the Carrier Tracking Loop, the
Symbol Tracking Loop and in the Lock Detector itself. The
Lock Detector can be configured either to make the “lock”
decision automatically using the State Machine Control
Mode, or to collect the necessary data so that an external
microprocessor can control the acquisition/tracking process
via the Microprocessor Control Mode (see Figure 22).
In State Machine Control Mode, the Lock Detector State
Machine monitors the outputs of the Phase Error Accumulator
and the False Lock Accumulator to determine the Lock
Detector state. Accumulation effectively averages the Phase
Error and false lock count, reducing their variance. Lock is
detected by accumulating the magnitude of the Phase Error
over a predetermined interval up to 1025 symbols (the
Integration Time). When the Carrier Loop is locked, the
Integration Period will end before an overflow occurs in the
Phase Error Accumulator. At the beginning of a lock detection
cycle, the Phase Error Accumulator and the Integration Counter
are loaded with their respective pre-load values. With each end
bit sample, the Phase Error Accumulator adds the magnitude of
the current Phase Error to its accumulated sum, while the
Integration Counter decrements one count. The Lock Detector
State Machine monitors the overflow bit of the Phase Error
Accumulator and the output of the Integration Counter. If the
Phase Error Accumulator overflows before the Integration
Counter reaches zero, then the accumulated Phase Error is too
large for the Carrier Tracking Loop to be in lock and the Lock
Detector State Machine goes into the Search state (see Lock
Detector State Machine in Figure 17). In the search state, the
loop parameters are reloaded with “Acquisition” rather than
“Tracking” values. When the Phase Accumulator overflows or
when the Integration Counter reaches zero, the Integration
Counter and the accumulators are re-initialized and the process
begins again. The Integration Counter Pre-load corresponds to
the number of symbols over which to integrate. The Phase
Error Preload corresponds to the distance the Phase Error
Accumulator starts away from overflow. This distance divided
by the Integration Period equals the average Phase Error. The
pre-load value is calculated using Equation 12:
Preload =
where
Full scale = 2
Full scale phase = 180° for CW, 90° for BPSK, 45° for QPSK,
etc;
Full Scale
–
⎛
⎝
18
---------------------------------------------- x 128 x Integration Count
Full Scale Phase
Lock Threshold
-1
24
⎞
⎠
(EQ. 12)
HSP50210
Lock Threshold <45° for BPSK, <22.5° for QPSK, etc.
(typical after shift); and Integration Count = Integration
Period measured in symbol times.
The False Lock Detector is used to indicate false lock on
square wave data in a high SNR environment. A false lock
condition is detected by monitoring the final integration stage
in the Q branch of the Integrate and Dump Filter (see
Figure 3 on page 7). If the magnitude of the integration over
the symbol period is less than the integration over half a
symbol period, a possible false lock condition is detected;
(integration over a symbol period has gone from end-bit to
end-bit, while integration over half the symbol period has
gone from the previous end-bit to mid-bit). By accumulating
the number of these occurrences over the Integration
Period, the Lock Detector State Machine determines
whether a false lock condition exists. The False Lock
Accumulator is used to accumulate the number of possible
false lock occurrences over the Integration Period. The
False Lock Accumulator can also be configured to
accumulate the output of the Frequency Error Detector (see
Lock Detection Configuration Control Register Bit 27:
Table 35 on page 40).
The Gain Error Accumulator provides a mechanism to
estimate data quality (E
the magnitude of the gain error of the end-bit samples, over
the Integration Period. Note: The Gain Error end-bit data is
valid only after lock has been declared, and the demod is
the tracking mode. The accumulated value gives an
indication of the variance about the ideal constellation
points. The accumulator output is read via the
Microprocessor Interface. The Gain Error Accumulator is
always pre-loaded with zero.
For applications where stepped acquisition is used, a Dwell
Counter is provided. In this mode, the lag accumulator in the
Carrier Loop Filter is stepped to a new frequency after each
Lock Detector integration. The Dwell Counter is used to hold
off Lock Accumulator integration until the loop has a chance
to settle.
Lock Detector Control
The selection of acquisition and tracking modes is controlled
by either the internal state machine or an external
microprocessor. The internal state machine monitors the
rollover of the Phase Error Accumulator and the False Lock
Accumulator relative to the Integration Counter. Depending
on whether the accumulators or counter roll over first, the
acquisition or tracking parameters are selected for the Loop
Filters and the Lock Detector Accumulators. In addition, the
state machine controls the frequency sweep input to the
Carrier Tracking Loop.
The flow of the acquisition control is shown in the State
Diagram in Figure 18 on page 26. The state machine
controls the acquisition process described as follows:
s
/N
o
). The accumulator integrates
July 2, 2008
FN3652.5