HSP50210JC-52 Intersil, HSP50210JC-52 Datasheet - Page 46

• Manufacturer Part Number: HSP50210JC-52
• Description: Digital Costas Loop 84-Pin PLCC
• Manufacturer: Intersil

Specifications of HSP50210JC-52

• Package: 84PLCC
• Power Supply Type: Analog
• Typical Supply Current: 225 mA
• Typical Operating Supply Voltage: 5 V
• Minimum Operating Supply Voltage: 4.75 V
• Maximum Operating Supply Voltage: 5.25 V

POSITION
POSITION
POSITION
31-16
15-6
BIT
N/A
BIT
BIT
2-0
5
4
3
6
5
4
3
2
1
0
Initialization of Lock
Detector Accumulators
Not Used
Reserved
Initialize NCO
Zero Symbol Tracking
Loop Filter
Accumulator
Zero Carrier Loop Filter
Accumulator
Reserved
Carrier Lock
Acquisition/Track
indicator
Reserved
Frequency Sweep
Direction
High Power
Low Power
Data Ready Strobe
FUNCTION
FUNCTION
FUNCTION
TABLE 45. INITIALIZE LOCK DETECTOR (μP CONTROL MODE) CONTROL REGISTER
46
Loading the address register with this destination address pre-loads all of the Lock Detector
Accumulators and resets the Integration Counters to restart the integration process. Note: A write to this
address only initializes the Lock Detector when it is in microprocessor control mode (see
Acquisition/Tracking Control Register; Table 38 on page 41).
No programming required.
Set to 0 for proper operation.
This bit is used to zero the feed back in the NCO’s phase accumulator. This is useful in setting the output
of the NCO to a known value.
0 = Enable normal NCO operation.
1 = Zero phase accumulator feedback for test.
This bit is used to zero the lag accumulator in the Symbol Tracking Loop Filter.
0 = Enable normal loop filter operation.
1 = Zero Lag Accumulator.
This bit is used to zero the lag accumulator in the Carrier Loop Filter.
0 = Enable normal loop filter operation.
1 = Zero Lag Accumulator.
Set to 0 for proper operation.
0 = Lock Detector is not in locked state (Carrier Tracking Loop is not locked).
1 = Lock Detector has achieved the locked state (Carrier lock has been achieved).
0 = Tracking Parameters currently being used by Tracking Loops.
1 = Acquisition Parameters currently being used by Tracking Loops.
N/A.
This bit indicates the direction of the frequency sweep selected by the Frequency Sweep input to the lag
path of the Carrier Tracking Loop Filter (Defined for upper sideband signals).
0 = Up (Sweep increasing in frequency).
1 = Down (Sweep decreasing in frequency).
This bit is one clock cycle long and indicates when the AGC is at its lower limit (see “AGC” on page 10
and Table 17 on page 33).
0 = AGC above lower limit.
1 = AGC at lower limit.
This bit is one clock cycle long and indicates when the AGC is at its upper limit (see “AGC” on page 10
and Table 17 on page 33).
0 = AGC is at or below its upper limit.
1 = AGC is above its upper limit.
This bit pulses “High” for one CLK synchronous with a new signal output on OUTB6-0 (see Output
Selector Control Register: Table 43 on page 44). For example if the lower 4 bits of the Output Selector
Register are set to 0010 (BINARY), This bit will pulse active on the same CLK that new FE7-1 data is
output.
TABLE 46. TEST CONFIGURATION CONTROL REGISTER
TABLE 47. STATUS 6-0 SIGNAL DESCRIPTIONS
DESTINATION ADDRESS = 30
DESTINATION ADDRESS = 31
HSP50210
DESCRIPTION
DESCRIPTION
DESCRIPTION
July 2, 2008
FN3652.5