74LV132PW NXP Semiconductors, 74LV132PW Datasheet - Page 17

• Manufacturer Part Number: 74LV132PW
• Description: Gates (AND / NAND / OR / NOR) QUAD 2-INPUT NAND SCHMITT TRIG
• Manufacturer: NXP Semiconductors

Specifications of 74LV132PW

• Product: NAND
• Logic Family: LV
• Number Of Gates: 4
• Number Of Lines (input / Output): 2 / 1
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Propagation Delay Time: 65 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-402
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Details
• Other names: 74LV132PW,112

NXP Semiconductors
20. Contents
1
2
3
4
5
6
6.1
6.2
7
8
9
10
11
12
13
14
15
16
17
18
18.1
18.2
18.3
18.4
19
20
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Transfer characteristics. . . . . . . . . . . . . . . . . . . 7
Waveforms transfer characteristics . . . . . . . . . 8
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Contact information. . . . . . . . . . . . . . . . . . . . . 16
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [e-mail]
Quad 2-input NAND Schmitt trigger
Document identifier: 74LV132_5
74LV132
Date of release: 2 July 2009
All rights reserved.