ICS83940DYI IDT, Integrated Device Technology Inc, ICS83940DYI Datasheet
ICS83940DYI
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ICS83940DYI Summary of contents
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... V 8 DDO Lead VFQFN 5mm x 5mm x 0.925mm package body K Package Top View ICS83940DYI REVISION C SEPTEMBER 7, 2010 Features • Eighteen LVCMOS/LVTTL outputs • Selectable LVCMOS_CLK or LVPECL clock inputs • PCLK, nPCLK pair can accept the following differential input levels: LVPECL, CML, SSTL • ...
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... R Input Pulldown Resistor PULLDOWN Power Dissipation Capacitance C PD (per output) R Output Impedance OUT ICS83940DYI REVISION C SEPTEMBER 7, 2010 Type Description Power Power supply ground. Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels. Clock select input. When HIGH, selects LVCMOS_CLK input. Input Pulldown When LOW, selects PCLK, nPCLK inputs ...
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... Biased; NOTE 1 0 – Biased; NOTE NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels. ICS83940DYI REVISION C SEPTEMBER 7, 2010 Clock LVCMOS_CLK De-selected Selected Outputs PCLK nPCLK Q[0:17 LOW 1 0 HIGH 0 Biased; NOTE 1 ...
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... V PP NOTE 1 Common Mode Input Voltage; V CMR NOTE Power Supply Current DD NOTE 1: V should not be less than -0.3V. IL NOTE 2: Common mode voltage is defined as V ICS83940DYI REVISION C SEPTEMBER 7, 2010 = V = 3.3V ± 5 -40°C to 85°C DD DDO A Test Conditions LVCMOS_CLK LVCMOS_CLK I = -20mA 20mA ...
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... V PP NOTE 1 Common Mode Input Voltage; V CMR NOTE Power Supply Current DD NOTE 1: V should not be less than -0.3V. IL NOTE 2: Common mode voltage is defined as V ICS83940DYI REVISION C SEPTEMBER 7, 2010 = V = 2.5V ± 5 -40°C to 85°C DD DDO A Test Conditions LVCMOS_CLK LVCMOS_CLK I = -12mA 12mA ...
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... NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V ICS83940DYI REVISION C SEPTEMBER 7, 2010 = V = 3.3V ± 5 -40° ...
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... NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V ICS83940DYI REVISION C SEPTEMBER 7, 2010 = 3.3V ± 5 2.5V ± 5%, T ...
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... NOTE 5: This parameter is defined in accordance with JEDEC Standard 65. NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at V ICS83940DYI REVISION C SEPTEMBER 7, 2010 = V = 2.5V ± 5 -40° ...
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... Core/2.5V LVCMOS Output Load AC Test Circuit Part 1 V DDO Qx 2 Part 2 V DDO Qy 2 tsk(pp) Part-to-Part Skew ICS83940DYI REVISION C SEPTEMBER 7, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 1.25V±5% SCOPE V DD, V DDO Qx LVCMOS GND -1.25V±5% 2.5V Core/2.5V LVCMOS Output Load AC Test Circuit ...
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... Q0:Q17 t R 3.3V Output Rise/Fall Time nPCLK PCLK LVCMOS_CLK V DDO Q0:Q17 Propagation Delay ICS83940DYI REVISION C SEPTEMBER 7, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER 2.4V 0.5V Q0:Q17 t F 2.5V Output Rise/Fall Time Q0:Q17 Output Duty Cycle/Pulse Width/Period 10 1.8V 1.8V 0. DDO ...
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... This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS83940DYI REVISION C SEPTEMBER 7, 2010 line impedance. For most 50Ω applications, R3 and R4 can be 100Ω ...
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... SSTL R1 120 Figure 2E. PCLK/nPCLK Input Driven by an SSTL Driver ICS83940DYI REVISION C SEPTEMBER 7, 2010 The input interfaces suggested here are examples only. If the driver and is from another vendor, use their termination recommendation. PP Please consult with the vendor of the driver component to confirm the driver termination requirements ...
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... All control pins have internal pullups or pulldowns; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. ICS83940DYI REVISION C SEPTEMBER 7, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER and dependent upon the package power dissipation as well as electrical conductivity requirements. Thus, thermal and electrical analysis and/or testing are recommended to determine the minimum number needed ...
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... Table 6B. vs. Air Flow Table for a 32 Lead VFQFN JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS83940DI is: 820 ICS83940DYI REVISION C SEPTEMBER 7, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER θ vs. Air Flow JA 0 200 47.9° ...
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... Basic D2 & E2 5.60 Ref. e 0.80 Basic L 0.45 0.60 θ 0° ccc Reference Document: JEDEC Publication 95, MS-026 ICS83940DYI REVISION C SEPTEMBER 7, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Maximum 1.60 0.15 1.45 0.45 0.20 0.75 7° 0.10 15 ©2010 Integrated Device Technology, Inc. ...
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... Minimum Nominal 0. 0.25 Ref. b 0.18 0.25 N & & E 5.00 Basic D2 & E2 3.0 e 0.50 Basic L 0.30 0.40 Reference Document: JEDEC Publication 95, MO-220 ICS83940DYI REVISION C SEPTEMBER 7, 2010 ( Anvil Anvil Singulation Singula tion (Ref.) N & N Odd Bottom View w/Type NOTE: The following package mechanical drawing is a generic drawing that applies to any pin count VFQFN package ...
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... Any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS83940DYI REVISION C SEPTEMBER 7, 2010 LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS/LVTTL FANOUT BUFFER Package ...
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... B T7B ICS83940DYI REVISION C SEPTEMBER 7, 2010 Description of Change Pin Characteristics table - changed R Delete R row. PULLUP 3.3V Output Load AC Test Circuit diagram - corrected GND equation to read -1.65V... from -1.165V... Added LVTTL to title. Updated format. Features Section - added Lead-Free bullet. Application Information Section - added Recommendations for Unused Input and Output Pins ...
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ICS83940DI Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to ...