MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 93

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

FOLV2 — Force output compare 2
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position
will force the OLV2 bit to the corresponding output level latch, thus appearing at the TCMP2 pin. Note
that this bit does not affect the OCF2 bit of the status register (see
FOLV1 — Force output compare 1
This bit always reads as zero, hence writing a zero to this bit has no effect. Writing a one at this position
will force the OLV1 bit to the corresponding output level latch, thus appearing at the TCMP1 pin. Note
that this bit does not affect the OCF1 bit of the status register (see
OLV2 — Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
IEDG1 — Input edge 1
When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the input capture register 1. When clear, a negative-going edge
triggers the transfer.
Note:
OLV1 — Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
MC68HC05X16
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
1 (set)
0 (clear) –
There is no need for an equivalent bit for the input capture register 2 as TCAP2 is
negative-going edge sensitive only.
Freescale Semiconductor, Inc.
–
–
–
–
–
For More Information On This Product,
OLV2 bit forced to output level latch.
No effect.
OLV1 bit forced to output level latch.
No effect.
A high output level will appear on the TCMP2 pin.
A low output level will appear on the TCMP2 pin.
TCAP1 is positive-going edge sensitive.
TCAP1 is negative-going edge sensitive.
A high output level will appear on the TCMP1 pin.
A low output level will appear on the TCMP1 pin.
Go to: www.freescale.com
PROGRAMMABLE TIMER
Section
Section
6.4.3).
6.4.3).
6-5
6