MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 113

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

R8 — Receive data bit 8
This read-only bit is the ninth serial data bit received when the SCI system is configured for nine
data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 0–7) are transferred from the serial
receive shift register to the SCI receive data register.
T8 — Transmit data bit 8
This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine
data bit operation (M = 1). When the eight low order bits (bits 0–7) of a transmit character are
transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred
to the ninth bit position of the shift register.
M — Mode (select character format)
The read/write M-bit controls the character length for both the transmitter and receiver at the same
time. The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity
bit (see
WAKE — Wake-up mode select
This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or
written to any time. See
MC68HC05X16
1 (set)
0 (clear) –
1 (set)
0 (clear) –
Table
x = Don’t care
WAKE
0
1
1
7-1).
Freescale Semiconductor, Inc.
–
–
For More Information On This Product,
(if M=0) or the 9th (if M=1) bit received on the Rx line is set.
or 12 (if M=1) consecutive ‘1’s on the Rx line.
Start bit, 9 data bits, 1 stop bit.
Start bit, 8 data bits, 1 stop bit.
Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th
Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M=0)
M
0
1
x
Table
SERIAL COMMUNICATIONS INTERFACE
Detection of an idle line allows the next data type received to cause the receive
data register to fill and produce an RDRF flag.
Detection of a received one in the eighth data bit allows an RDRF flag and
associated error flags.
Detection of a received one in the ninth data bit allows an RDRF flag and
associated error flags.
Table 7-1 Method of receiver wake-up
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7-1.
Method of receiver wake-up
7-11
7