MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 40

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

2
2.3.15
The VPP1 pin is the output of the charge pump for the EEPROM1 array.
2.3.16
The VRH pin is the positive reference voltage for the A/D converter.
2.3.17
The VRL pin is the negative reference voltage for the A/D converter.
2.3.18
These 24 I/O lines comprise ports A, B and C. The state of any pin is software programmable, and
all the pins are configured as inputs during power-on or reset.
Under software control the PC2 pin can output the internal E-clock (see
Resistive pull downs are provided on port B and/or port C and can be enabled via a mask option
(see
Section
2.3.19
This pin provides another wired-OR interrupt capability in addition to port B. Wired-OR interrupts
are requested when this pin is pulled high (if wired-OR interrupts are enabled), i.e. interrupt
sensitivity on this pin is complementary to sensitivity on the IRQ pin (see
Section
conditions. It is not necessary to tie NWOI to V
present.
2.3.20
This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D
converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is
disabled which forces the port D pins to be input only port pins (see
Section
10.2.3.3).
10.2.3.1). When this pin is not in use it is recommended that it be tied to V
1.2). Wired-OR interrupt capability is provided on all pins of port B (see
VPP1
VRH
VRL
PA0 – PA7/PB0 – PB7/PC0 – PC7
NWOI
PD0/AN0–PD7/AN7
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SS
when there is a negligible amount of noise
Section
Section
9.5).
4.2).
MC68HC05X16
Table 10-3
SS
in noisy
Rev. 1
in