MC68HC705X32CFU Freescale Semiconductor, MC68HC705X32CFU Datasheet - Page 146

• Manufacturer Part Number: MC68HC705X32CFU
• Manufacturer: Freescale Semiconductor

Specifications of MC68HC705X32CFU

• Cpu Family: HC05
• Device Core Size: 8b
• Frequency (max): 4MHz
• Interface Type: SCI
• Program Memory Type: EPROM
• Program Memory Size: 32KB
• Total Internal Ram Size: 528Byte
• # I/os (max): 32
• Number Of Timers - General Purpose: 1
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 4.5V
• On-chip Adc: 8-chx8-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: PQFP
• Lead Free Status / Rohs Status: Supplier Unconfirmed

10
Error IRQ:
Data overrun: an incoming message on the bus cannot be received because both receive buffers
Wake-up IRQ: this signals activity on the bus while the MCAN is in SLEEP mode. This is the only
CIRQ interrupts are serviced by the routine located at the address specified by the contents of
$3FF0 and $3FF1.
10.2.3.4
There are five different timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a
timer interrupt whenever they are set and enabled. These five interrupt flags are found in the five
most significant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will vector
to the service routine defined by $3FF8-$3FF9, OCF1 and OCF2 will vector to the service routine
defined by $3FF6–$3FF7 and TOF will vector to the service routine defined by $3FF4–$3FF5 as
shown in
There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,
and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address
$0012. See
10.2.3.5
There are five different interrupt flags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts
whenever they are set and enabled. These five interrupt flags are found in the five most significant
bits of the SCI status register (SCSR) at location $0010.
There are four corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and
ILIE for IDLE. These enable bits are located in the serial communications control register 2
(SCCR2) at address $000F. See
The SCI interrupt causes the program counter to vector to the address pointed to by memory
locations $3FF2 and $3FF3 which contain the starting address of the interrupt service routine.
Software in the SCI interrupt service routine must determine the priority and cause of the interrupt
by examining the interrupt flags and the status bits located in the serial communications status
register SCSR (address $0010).
The general sequence for clearing an interrupt is a software sequence of accessing the serial
communications status register while the flag is set followed by a read or write of an associated
register. Refer to
Figure
Section 6.2.1
Timer interrupts
Serial communications interface (SCI) interrupts
this is set when either the error status or bus status bits in the MCAN status register
change state (see
are tied up.
nonmaskable CIRQ.
6-1.
Section 7
Freescale Semiconductor, Inc.
For More Information On This Product,
and
for a description of the SCI system and its interrupts.
Section 6.2.2
Section 7.11.3
RESETS AND INTERRUPTS
Section
Go to: www.freescale.com
5.3.3).
for further information.
and
Section
7.11.4.
MC68HC05X16
Rev. 1