AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 51

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

cles to either SMM space or normal memory space. This
can be accomplished by saving the status of SMIACT
with the address for each word in the write buffers.
6.8.6 Nested SMI and I/O Restart
Special care must be taken when executing an SMI han-
dler for the purpose of restarting an l/O instruction. When
the CPU executes a Resume (RSM) instruction with the
l/O restart slot set, the restored EIP is modified to point
to the instruction immediately preceding the SMI re-
quest, so that the l/O instruction can be re-executed. If
a new SMI request is received while the CPU is execut-
ing an SMI handler, the CPU services this SMI request
before restarting the original I/O instruction. If the I/O
restart slot is set when the CPU executes the RSM in-
struction for the second SMI handler, the RSM micro-
code decrements the restored EIP again. EIP then
points to an address different from the originally inter-
rupted instruction, and the CPU begins execution at an
incorrect entry point. To prevent this from occurring, the
SMI handler routine must not set the I/O restart slot
during the second of two consecutive SMI handlers.
6.9
6.9.1 SMM Code Considerations
The default operand size and the default address size
are 16 bits; however, operand-size override and ad-
dress-size override prefixes can be used as needed to
directly access data anywhere within the 4-Gbyte logical
address space.
With operand-size override prefixes, the SMI handler
can use jumps, calls, and returns to transfer a control
to any location within the 4-Gbyte space. Note, however,
the following restrictions:
1. Any control transfer that does not have an operand-
2. Due to the Real mode style of base-address formation,
6.9.2 Exception Handling
Upon entry into SMM, external interrupts that require
handlers are disabled (the IF in EFLAGS is cleared).
This is necessary because, while the processor is in
SMM, it is running in a separate memory space. Con-
sequently, the vectors stored in the interrupt descriptor
table (IDT) for the prior mode are not applicable. Before
allowing exception handling (or software interrupts), the
SMM program must initialize new interrupt and excep-
tion vectors. The interrupt vector table for SMM has the
same format as for Real mode. Until the interrupt vector
table is correctly initialized, the SMI handler must not
generate an exception (or software interrupt). Even
though hardware interrupts are disabled, exceptions
and software interrupts can still occur. Only a correctly
written SMI handler can prevent internal exceptions.
size override prefix truncates EIP to 16 Low-order bits.
a long jump or call cannot transfer control segment
with a base address of more than 20 bits (1 Mbyte).
SMM Software Considerations
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
When new exception vectors are initialized, internal ex-
ceptions can be serviced. Restrictions are as follows:
1. Due to the Real mode style of base address forma-
2. An interrupt or exception cannot transfer control to
3. If exceptions or interrupts are allowed to occur, only
4. The SMBASE Relocation feature affects the way
Note: The execution of an IRET instruction enables
Non-Maskable Interrupt (NMI) processing.
6.9.3 Halt During SMM
HALT should not be executed during SMM, unless in-
terrupts have been enabled. Interrupts are disabled on
entry to SMM. INTR and NMI are the only events that
take the CPU out of HALT within SMM.
6.9.4 Relocating SMRAM to an Address Above
Within SMM (or Real mode), the segment base registers
can be updated only by changing the segment register.
The segment registers contain only 16 bits, which allows
only 20 bits to be used for a segment base address (the
segment register is shifted left 4 bits to determine the
segment base address). If SMRAM is relocated to an
address above 1 Mbyte, the segment registers can no
longer be initialized to point to SMRAM.
These areas can still be accessed by using address
override prefixes to generate an offset to the correct
address. For example, if the SMBASE has been relo-
cated immediately below 16 Mbyte, the DS and ES reg-
isters are still initialized to 0000 0000h. Data in SMRAM
can still be accessed by using 32-bit displacement reg-
isters.
move esi,OOFFxxxxh
move ax,ds:[esi]
7
The Cache Test Registers for the Enhanced Am486DX
microprocessors are the same test registers (TR3, TR4,
and TR5) provided in all Am486 microprocessors. TR3
is the cache test data register. TR4, the cache test status
register, and TR5, the cache test control register, oper-
ate together with TR3.
tion, an interrupt or exception cannot transfer con-
trol to a segment with a base address of more than
20 bits.
a segment offset of more than 16 bits.
the Low order 16 bits of the return address are
pushed onto the stack. If the offset of the interrupted
procedure is greater than 64 Kbyte, it is not possible
for the interrupt/exception handler to return control
to that procedure. (One work-around is to perform
software adjustment of the return address on the
stack.)
the CPU returns from an interrupt or exception dur-
ing an SMI handler.
1 Mbyte
TEST REGISTERS 4 AND 5
MODIFICATIONS
;64K segment
immediately below 16M
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