AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 35

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

At this point the CPU is in the Stop Grant state.
The CPU cannot respond to a STPCLK request from an
HLDA state because it cannot empty the write buffers
and, therefore, cannot generate a Stop Grant cycle. The
rising edge of STPCLK signals the CPU to return to
program execution at the instruction following the inter-
rupted instruction. Unlike the normal interrupts (INTR
and NMI), STPCLK does not initiate interrupt acknowl-
edge cycles or interrupt table reads.
4.2.1 External Interrupts in Order of Priority
In Write-through mode, the priority order of external in-
terrupts is:
1. RESET/SRESET
2. FLUSH
3. SMI
4. NMI
5. INTR
6. STPCLK
In Write-back mode, the priority order of external inter-
rupts is:
1. RESET
2. FLUSH
3. SRESET
4. SMI
5. NMI
6. INTR
7. STPCLK
STPCLK is active Low and has an internal pull-up re-
sistor. STPCLK is asynchronous, but setup and hold
times must be met to ensure recognition in any specific
clock. STPCLK must remain active until the Stop Grant
special bus cycle is asserted and the system responds
with either RDY or BRDY. When the CPU enters the
Stop Grant state, the internal pull-up resistor is disabled,
reducing the CPU power consumption. The STPCLK
input must be driven High (not floated) to exit the Stop
Grant state. STPCLK must be deasserted for a minimum
of five clocks after RDY or BRDY is returned active for
the Stop Grant bus cycle before being asserted again.
There are two regions for the Low-power mode supply
current:
1. Low Power: Stop Grant state (fast wake-up, frequency-
2. Lowest Power: Stop Clock state (slow wake-up, volt-
Empties all internal pipelines and write buffers
Generates a Stop Grant bus cycle
Stops the internal clock
and voltage-dependent)
age-dependent)
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
4.3
The processor drives a special Stop Grant bus cycle to
the bus after recognizing the STPCLK interrupt. This
bus cycle is the same as the HALT cycle used by a
standard Am486 microprocessor, with the exception
that the Stop Grant bus cycle drives the value 0000
0010h on the address pins.
The system hardware must acknowledge this cycle by
returning RDY or BRDY, or the processor will not enter
the Stop Grant state (see Figure 19). The latency be-
tween a STPCLK request and the Stop Grant bus cycle
depends on the current instruction, the amount of data
in the CPU write buffers, and the system memory per-
formance.
4.4
Table 10 shows the pin states during Stop Grant Bus
states. During the Stop Grant state, most output and
input/output signals of the microprocessor maintain the
level they held when entering the Stop Grant state. The
data and data parity signals are three-stated. In re-
sponse to HOLD being driven active during the Stop
Grant state (when the CLK input is running), the CPU
generates HLDA and three-states all output and input/
output signals that are three-stated during the HOLD/
HLDA state. After HOLD is deasserted, all signals return
to the same state they were before the HOLD/HLDA
sequence.
A3–A2
A31–A4
D31–D0
BE3–BE0
DP3–DP0
W/R, D/C, M/IO, CACHE
ADS
LOCK, PLOCK
BREQ
HLDA
BLAST
FERR
PCHK
SMIACT
HITM
Table 10. Pin State During Stop Grant Bus State
M/lO = 0
D/C = 0
W/R =1
Address Bus = 0000 0010h (A
BE3–BE0 = 1011
Data bus = undefined
Stop Grant Bus Cycle
Pin State During Stop Grant
Signal
Type
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
4
= 1)
Previous State
Previous State
Floated
Previous State
Floated
Previous State
Inactive
Inactive
Previous State
As per HOLD
Previous State
Previous State
Previous State
Previous State
Previous State
State
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