AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 42

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

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6.3.4 SMRAM State Save Map
When SMI is recognized on an instruction boundary, the
CPU core first sets the SMIACT signal Low, indicating
to the system logic that accesses are now being made
to the system-defined SMRAM areas. The CPU then
writes its state to the state save area in the SMRAM.
The state save area starts at SMBASE + [8000h +
7FFFh]. The default CS Base is 30000h; therefore, the
default state save area is at 3FFFFh. In this case, the
CS Base is also referred to as the SMBASE.
If the SMBASE relocation feature is enabled, the
SMRAM addresses can change. The following formula
is used to determine the relocated addresses where the
context is saved: SMBASE + [8000h + Register Offset],
where the default initial SMBASE is 30000h and the
Register Offset is listed in Table 11. Reserved spaces
are for new registers in future CPUs. Some registers in
the SMRAM state save area may be read and changed
by the SMI handler, with the changed values restored
to the processor register by the RSM instruction. Some
register images are read-only, and must not be modified.
(Modifying these registers results in unpredictable
behavior.) The values stored in the “reserved” areas
may change in future CPUs. An SMI handler should not
rely on values stored in a reserved area.
The following registers are written out during SMSAVE
mode to the RESERVED memory locations (7FA7h–
7F98h, 7F93h–7F8Ch, and 7F87h–7F08h), but are not
visible to the system software programmer:
If an SMI request is issued to power down the CPU, the
values of all reserved locations in the SMM state save
area must be saved to non-volatile memory.
The following registers are not automatically saved and
restored by SMI and RSM:
Note: You can save the FPU state by using an FSAVE
or FNSAVE instruction.
DR3–DR0
CR2
CS, DS, ES, FS, GS, and SS hidden descriptor
registers
EIP_Previous
GDT Attributes and Limits
IDT Attributes and Limits
LDT Attributes, Base, and Limits
TSS Attributes, Base, and Limits
TR7–TR3
FPU registers:
— STn
— FCS
— FSW
— Tag Word
— FP instruction pointer
— FP opcode
— Operand pointer
Enhanced Am486DX Microprocessor Family
P R E L I M I N A R Y
For all SMI requests except for power down suspend/
resume, these registers do not have to be saved be-
cause their contents will not change. During a power
down suspend/resume, however, a resume reset clears
these registers back to their default values. In this case,
the suspend SMI handler should read these registers
directly to save them and restore them during the power
up resume. Anytime the SMI handler changes these
registers in the CPU, it must also save and restore them.
Note:
*Upper 2 bytes are not modified.
7FA7h–7F98h Reserved
7F93h–7F8Ch Reserved
7EF7h–7E00h Reserved
7F87h–7F08h Reserved
Register
Offset*
7FFCh
7FECh
7FDCh
7FCCh
7FBCh
7FACh
7EFCh
7FE8h
7FE4h
7FE0h
7FD8h
7FD4h
7FD0h
7FC8h
7FC4h
7FC0h
7FB8h
7FB4h
7FB0h
7FA8h
7EF8h
7FF8h
7FF4h
7FF0h
7F94h
7F88h
7F04h
7F02h
7F00h
Table 11. SMRAM State Save Map
CRO
CR3
EFLAGS
EIP
EDI
ESI
EBP
ESP
EBX
EDX
ECX
EAX
DR6
DR7
TR*
LDTR*
GS*
FS*
DS*
SS*
CS*
ES*
IDT Base
GDT Base
I/O Trap Word
Halt Auto Restart
I/O Trap Restart
SMM Revision Identifier
State Dump Base
Register
Writable?
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No