AM486DX2-66V16BHC AMD (ADVANCED MICRO DEVICES), AM486DX2-66V16BHC Datasheet - Page 20

• Manufacturer Part Number: AM486DX2-66V16BHC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM486DX2-66V16BHC

• Family Name: Am486
• Device Core Size: 32b
• Frequency (max): 66MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: SQFP
• Lead Free Status / Rohs Status: Not Compliant

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If the PWT signal is 0, the external WB/WT signal de-
termines the new state of the line. If the WB/WT signal
was asserted to 1 during reload, the line transits to the
exclusive state. If the WB/WT signal was 0, the line
transits to the shared state. If the PWT signal is 1, it
overrides the WB/WT signal, forcing the line into the
shared state. Therefore, if paging is enabled, the soft-
ware programmed PWT bit can override the hardware
signal WB/WT.
Until the line is reallocated, a write is the only processor
action that can change the state of the line. If the write
occurs to a line in the exclusive state, the data is simply
written into the cache and the line state is changed to
modified. The modified state indicates that the contents
of the line require copy-back to the main memory before
the line is reallocated.
If the write occurs to a line in the shared state, the cache
performs a write of the data on the external bus to update
the external memory. The line remains in the shared
state until it is replaced with a new cache line or until it
is flushed. In the modified state, the processor continues
to write the line without any further external actions or
state transitions.
If the PWT or PCD bits are changed for a specified mem-
ory location, the tag bits in the cache are assumed to
be correct. To avoid memory inconsistencies with re-
spect to cacheability and write status, a cache copy-
back and invalidation should be invoked either by using
the WBINVD instruction or asserting the FLUSH signal.
3.8.2 Snooping Actions and State Transitions
To maintain cache coherency, the CPU must allow
snooping by the current bus master. The bus master
initiates a snoop cycle to check whether an address is
cached in the internal cache of the microprocessor. A
snoop cycle differs from any other cycle in that it is ini-
Read_Hit
Figure 1. Processor-Induced Line Transitions in
Read_Miss
(WB/WT = 1)
(PWT = 0)
Exclusive
Write_Hit
Write-Back Mode
Read_Hit
+ Write_Hit
Modified
Invalid
Write_Hit + Read_Hit
Enhanced Am486DX Microprocessor Family
Read_Miss
[(WB/WT = 0) + (PWT = 1)
Note: Write_Hit
generates external
bus cycle.
Shared
Shared
P R E L I M I N A R Y
tiated externally to the microprocessor, and the signal
for beginning the cycle is EADS instead of ADS. The
address bus of the microprocessor is bidirectional to
allow the address of the snoop to be driven by the sys-
tem. A snoop access can begin during any hold state:
In the clock in which EADS is asserted, the micropro-
cessor samples the INV input to qualify the type of in-
quiry. INV specifies whether the line (if found) must be
invalidated (i.e., the MESI status changes to Invalid or
I). A line is invalidated if the snoop access was generated
due to a write of another bus master. This is indicated
by INV set to 1. In the case of a read, the line does not
have to be invalidated, which is indicated by INV set to 0.
The core system logic can generate EADS by watching
the ADS from the current bus master, and INV by watch-
ing the W/R signal. The microprocessor compares the
address of the snoop request with addresses of lines in
the cache and of any line in the copy-back buffer waiting
to be transferred on the bus. It does not, however, com-
pare with the address of write-miss data in the write
buffers. Two clock cycles after sampling EADS, the mi-
croprocessor drives the results of the snoop on the HITM
pin. If HITM is active, the line was found in the modified
state; if inactive, the line was in the exclusive or shared
state, or was not found.
Figure 2 shows a diagram of the state transitions in-
duced by snooping accesses.
(EADS = 0 * INV = 1)
+ FLUSH = 0
(HITM asserted
+ write-back)
While HOLD and HLDA are asserted
While BOFF is asserted
While AHOLD is asserted
EADS = 0 * INV = 1
+ FLUSH = 0
Exclusive
Figure 2. Snooping State Transitions
EADS = 0 * INV = 0
* FLUSH = 1
(HITM asserted
+ write-back)
EADS = 0 * INV = 0
* FLUSH = 1
Modified
Invalid
(EADS = 0 * INV = 1)
+ FLUSH = 0
EADS = 0 * INV = 0
* FLUSH = 1
Shared