ICS1522M IDT, Integrated Device Technology Inc, ICS1522M Datasheet
ICS1522M
Specifications of ICS1522M
Available stocks
Related parts for ICS1522M
ICS1522M Summary of contents
Page 1
Integrated Circuit Systems, Inc. User-Programmable Video Clock Generator/ Line-Locked Clock Regenerator General Description The ICS1522 is a very high performance monolithic phase- locked loop (PLL) frequency synthesizer. Utilizing ICS’s advanced CMOS mixed-mode technology, the ICS1522 provides a low-cost solution for ...
Page 2
ICS1522 Overview The ICS1522 is ideally suited to provide the graphics system clock signals required by high-performance video DACs. Fully programmable feedback and reference divider capability allow virtually any frequency to be generated, not just simple multiples of the reference ...
Page 3
Output Description The differential output drivers, CLK+ and CLK-, are current-mode and are designed to drive resistive terminations in a complementary fashion. The outputs are current- sinking only, with the amount of sink current programmable via the IPRG pin. The ...
Page 4
ICS1522 Power-On Initialization The ICS1522 has an internal power-on reset circuit that sets the frequency of the CLK+and CLK- outputs to be half the crystal or reference frequency assuming that they are between 10 MHz and 25 MHz (refer to ...
Page 5
ICS1522 Register Definition REG# BIT(S) BIT REF. 0 0-10 F[0:10] 1 0-7 LO[0:7] 2 0-7 HI[0:7] 3 0-9 R[0: REF_POL 4 0-2 VCO[0:2] DESCRIPTION Feedback Divider (Default=04F, Modulus=80) Divides the VCO by the set modulus Modulus Range=64 to ...
Page 6
ICS1522 REG# BIT(S) BIT REF. 4 3-5 PFD (0; PDEN 4 7 INT_FLT 4 8 INT_VCO 4 9 CLK_SEL 4 10 RESERVED 5 0 FBK_SEL 5 1 FBK_POL 5 2 ADD 5 3 SWLW DESCRIPTION Phase Frequency Detector ...
Page 7
REG# BIT(S) BIT REF. 5 4-5 PDA(0:1) 5 6-7 PDB(0: LD_LG 5 9 F_EN 5 10 RESERVED 6 0-2 L(0:2) DESCRIPTION Output Post-scaler (Default=0) Input=VCO; Output = Differential Output PFD(2) PFD( ...
Page 8
ICS1522 REG# BIT(S) BIT REF OMUX1 6 4 OMUX2 6 5 OMUX3 6 6 OMUX4 6 7 DACRST 6 8 AUXEN 6 9 AUXCLK 6 10 EXTREF DESCRIPTION OUT1 Select (Default=0) 0=Load Counter Output 1=Diff. Output Divided by ...
Page 9
Serial Programming Timing Diagram NOTES: 1. R/Wn, READ=1 and WRITE=0 2. Address and data transmitted least significant bit first 3. 16 Positive-edge clocks required for complete data read/write (1-R/Wn, 3-Address, 11-Data, and 1 load data W/SELn HIGH) 4. SELn’s positive ...
Page 10
ICS1522 Absolute Maximum Ratings VDD, VDDO (measured to VSS) ................. 7.0V Digital Inputs VSS ....................................... -0.5 to VDD to 0.5V Digital Outputs VSS ..................................... -0.5 to VDDO to +0.5V Storage temperature .................................... -65 to 150 ° Characteristics Junction ...
Page 11
AC Characteristics SYMBOL PARAMETER Fvco VCO Frequency Fxtal Crystal Frequency Cpar Crystal Oscillator Loading Capacitance FHSYNC Horizontal Sync Rate Txhi XTAL1 High Time (when driven externally) Txlo XTAL1 Low Time (when driven externally) TJIT Phase Jitter (see Note 1) Tlock ...
Page 12
ICS1522 Memory Definition ICS1522 memory is loaded serially with the least significant bit clocked into the device first. After the R/Wn bit, the next three bits of the programming word (15 bits) hold the memory location to be loaded. The ...
Page 13
... Initial synchronization is accomplished by switching from the external feedback source (graphics system HSYNC) to the internal feedback. Let us assume that we are now using the internal divider. Ordering Information ICS1522MLF Example: ICS XXXX MLF Package Type Device Type (consists digit numbers) ...