LH28F160BVHE-BTL90 Sharp Electronics, LH28F160BVHE-BTL90 Datasheet - Page 22

• Manufacturer Part Number: LH28F160BVHE-BTL90
• Manufacturer: Sharp Electronics

Specifications of LH28F160BVHE-BTL90

• Cell Type: NOR
• Density: 16Mb
• Access Time (max): 90ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 21/20Bit
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 2M/1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Not Compliant

The device will often be used in large memory arrays.
To use these control inputs efficiently, an address decoder
should enable CE# while OE# should be connected to all
memory devices and the system’s READ# control line.
This assures that only selected memory devices have
active outputs while deselected memory devices are in
standby mode. RP## should be connected to the system
POWERGOOD
system power transitions.
toggle during system reset.
5.2 RY/BY#, Block Erase and Word/Byte
RY/BY# is an open drain output that should be connected
to V,, by a pulllup resistor to provide a hardware method
of detecting block erase and word/byte write completion.
[t transitions low after block erase or word/byte write
commands and returns to High Z when the WSM has
finished executing the internal algorithm.
RY/BY#
system CPU or controller. It is active at all times. RY/BY#
is also High Z when the device is in block erase suspend
(with word/byte write inactive), word/byte write suspend
3r deep power-down
5 DESIGN CONSIDERATIONS
5.1 Three-Line Output Control
SHARP provides three control inputs to accommodate
multiple memory connections. Three-line control provides
for:
b. Complete assurance that data bus contention will not
a. Lowest possible memory power dissipation.
SHARP
occur.
Write Polling
can be connected to an interrupt input of the
signal to prevent unintended writes during
modes.
POWERGOOD
should also
LHF16Vll
inductive loading. Two-line control and proper decoupling
Each device should have a O.l@
connected between its V,,
capacitors should be placed as close as possible to package
leads. Additionally,
electrolytic capacitor should be placed at the array’s powex
supply connection between V,,
capacitor will
board trace inductance.
5.4 Vpp Trace on Printed Circuit Boards
Updating flash memories that reside in the target system
requires that the printed circuit board designer pay
attention to the V,,
supplies the memory cell current for word/byte writing
and block erasing. Use similar trace widths and layout
considerations given to the V,, power bus. Adequate V,,
supply traces and decoupling will decrease V,, voltage
spikes and overshoots.
5.3 Power Supply Decoupling
Flash memory power switching
careful device decoupling. System designers are interested
in three supply current issues: standby current levels.
active current levels and transient peaks produced by
falling and rising edges of CE# and OE#. Transient cm-rem
magnitudes depend on the device outputs’ capacitive and
capacitor selection will suppress transient voltage peaks.
and GND.
These
overcome voltage slumps caused by PC
for every eight devices, a 4.7pF
Power supply trace. The V,, pin
high-frequency,
and GND and between its V,,
characteristics
and GND. The bulk
ceramic capacitor
low
inductance
Rev. 1.1
require
20