LH28F160BVHE-BTL90 Sharp Electronics, LH28F160BVHE-BTL90 Datasheet

no-image

LH28F160BVHE-BTL90

Manufacturer Part Number
LH28F160BVHE-BTL90
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F160BVHE-BTL90

Cell Type
NOR
Density
16Mb
Access Time (max)
90ns
Interface Type
Parallel
Boot Type
Bottom
Address Bus
21/20Bit
Operating Supply Voltage (typ)
3.3V
Operating Temp Range
-40C to 85C
Package Type
TSOP
Sync/async
Asynchronous
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (max)
3.6V
Word Size
8/16Bit
Number Of Words
2M/1M
Supply Current
30mA
Mounting
Surface Mount
Pin Count
48
Lead Free Status / Rohs Status
Not Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LH28F160BVHE-BTL90
Manufacturer:
SHARP
Quantity:
7 333
Part Number:
LH28F160BVHE-BTL90
Manufacturer:
SHARP
Quantity:
1 000
Part Number:
LH28F160BVHE-BTL90
Manufacturer:
SHARP
Quantity:
1 000
Part Number:
LH28F160BVHE-BTL90
Manufacturer:
SHARP
Quantity:
20 000
P
P
S
RELIMINARY
RODUCT
PECIFICATIONS
Integrated Circuits Group
®
LH28F160BVHE-BTL90
Flash Memory
16M (2M ×8/1M x 16)
(Model No.: LHF16V11)
Spec No.: EL10Y079A
Issue Date: September 8, 1999

Related parts for LH28F160BVHE-BTL90

LH28F160BVHE-BTL90 Summary of contents

Page 1

... P P RELIMINARY RODUCT LH28F160BVHE-BTL90 S PECIFICATIONS ® Flash Memory 16M (2M ×8/1M x 16) (Model No.: LHF16V11) Spec No.: EL10Y079A Issue Date: September 8, 1999 Integrated Circuits Group ...

Page 2

Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. *When using the products covered herein, please ...

Page 3

SHARI= ........................................................... .3 1 INTRODUCTION.. 1.1 Features ........................................................................ 3 1.2 Product Overview.. ...................................................... .3 2 PRINCIPLES OF OPERATION.. ..................................... .7 2.1 Data Protection ............................................................ . ............................................................ 8 3 BUS OPERATION 3.1 Read.. ........................................................................... .8 3.2 Output Disable .............................................................. 8 3.3 ...

Page 4

... Its enhanced suspend capabilities provide for an ideal solution for code + data storage applications. For secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to DRAM, the LH28F160BVHE-BTL90 protection with V,, at GND, selective hardware boot block locking. These alternatives give designers ultimate control of their code security needs. is manufactured on SHARP’ ...

Page 5

... SHARP 1 INTRODUCTION This datasheet contains LH28F160BVHE-BTL90 specifications. Section 1 provides a flash memory overview. Sections 2,3,4 and 5 describe the memory organization and functionality. Section 6 covers electrical specifications. 1.1 Features Key enhancements of LH28F160BVHE-BTL90 memory are: l 2.7V-3.6V V,, and V,, Read/Write/Erase Operations *Enhanced Suspend Capabilities l Boot Block Architecture ...

Page 6

SHARI= The boot blocks can be locked for the WP# pin. Block erase or word/byte write for boot block must not be carried out by WP# to Low and RP# to V,,. The status register indicates when the WSM’s block ...

Page 7

SHARP Al5 AM A13 AI? 8 AII 6 Alo I A9 ‘48 9 AI9 WE# RF% 13 VPP 14 WP# 15 RYlBY# 16 ‘418 17 A17 ‘ ...

Page 8

... V,, (see DC Characteristics) produce spurious results and should not be attempted. DEVICE POWER SUPPLY: Do not float any power pins. With VcclV,,O, SUPPLY the flash memory are inhibited. Device operations at invalid V,, voltage (see DC Characteristics) VCC produce spurious results and should not be attempted. SUPPLY GND GROUND: Do not float any ground pins ...

Page 9

... SHARP 0F 2 PRINCIPLES OPERATION The LH28F160BVHE-BTL90 Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for: 100% l-IL-level fixed power supplies during block erasure and word/byte write, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from deep power- down mode (see Bus Operations), the device defaults to read array mode ...

Page 10

... Refer to Table 6 for write protection alternatives. 3 BUS OPERATION The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 Read Information can be read from any block, identifier codes or status register independent of the V,, voltage ...

Page 11

Read Identifier Codes Operation The read identifier codes operation manufacturer code and device code (see Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms. IAi& ...

Page 12

Notes Mode ‘I, 8 Read vIH Output Disable 10 $Ior Standby Deep Power-Down 4,lO 8 ‘+H Or Read Identifier Codes ‘1, Write 6,7,8 ,. Notes Mode 8 v*Hor Read VHH vIH Output Disable VI-II-I vIH Standby 10 VHH 4,lO Deep ...

Page 13

SHARP NOTES: 1. BUS operations are defined in Table 3.1 and Table 3.2. 2. X=Any valid address within the device. IA=Identifier Code Address: see Figure 4. A-, set V,, in Byte Mode (BYTE#=V,). BA=Address within the block ...

Page 14

SHARP 4.1 Read Array Command Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by-writing command. The device remains enabled for reads until another command is ...

Page 15

... The only other valid commands while block erase is or RP#=V,. suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block operations with erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/BY# will return to VOL ...

Page 16

... Vpp=Vr for Complete Protection The V,, programming complete write protection of all blocks in the flash device. 4.10.2 WP#=V,L for Block Locking The lockable blocks are locked when WP#=V,; program or erase operation to a locked block will result in an error, which will be reflected in the status register. For is top configuration, the top two boot blocks are lockable ...

Page 17

SHARI= 1 WSMS 1 ESS SR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 ...

Page 18

SHARI= Suspnd Check if Desired FLU STATUS CHECK PROCEDURE Read Status Register Da&See Above) Device Protect Error Command Sequence Block Erase Error Block Emse Successful Figure 5. Automated LHF16Vll Command W&e Erase setup Erase Write COdUlll Read I Block Standby ...

Page 19

SHARP Write 4OH or IOH. Suspend Word/Byte writs Lmp FULL STATUS CHECK PROCEDURE Read Status Register Data(See Above) Device Proten Error Figure 6. Automated Word/Byte Write Flowchart LHl716Vll BUS Command Opsrarion Data&OH or IOH Write Setup Word&e Write Addr=Location Data=D.ua ...

Page 20

SHARI= Write BOH Word/Byte Write Loop Figure 7. Block Erase Suspend/Resume Flowchart . LHFl6Vll I=Block Era.sss Suspended Rev. 1.02 ...

Page 21

LHF16Vll BUS operation Read Standby Read write Figure 8. Word/Byte Write Suspend/Resume Flowchart . Comments Command Data=BOH Addr=X Status Register Data Add,=X I Check SR.2 I=Wocd/Bpe Write Suspended O=Word/Bpe Write Completed Red Array iocauons other than hat bang written. I ...

Page 22

... PC board trace inductance. 5.4 Vpp Trace on Printed Circuit Boards should also Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the V,, supplies the memory cell current for word/byte writing and block erasing ...

Page 23

... Power Dissipation When designing portable systems, designers must consider battery power operation, but also for data retention during system idle time. Flash memory’s battery life because data is retained when system power is removed. In addition, deep power-down low power consumption even when system power is applied ...

Page 24

ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings* Operating Temperature During Read, Block Erase and Word/Byte Write . . . . . .._...................... -40°C to +85”C(‘) Temperature under Bias . . . . . . .._............. -40°C to +85”C Storage Temperature ...

Page 25

SHARP 6.2.2 AC INPUT/OUTPUT TEST CONDITIONS AC test inputs are driven at 2.7V for a Logic “1” and O.OV for a Logic “0.” Input timing begins, and output timing ends, at 1.35V. Input rise and fail times (10% to 90%) ...

Page 26

SI-IARP 52.3 DC CHARACTERISTICS SW. Parameter Input Load Current IL1 Output Leakage Current IL0 ICC, Vcc Standby Current Vcc Deep Power-Down Current ICCD Vcc Read Current ICCR V,, Word/Byte Write Current ICCW V,, Block Erase Current ICCE V,, Word/Byte Write ...

Page 27

JOTES: . All currents are in RMS unless otherwise noted. Typical values at nominal V,, voltage and T,=+25”C. are specified with the device de-selected. If read or word/byte written while in erase suspend mode ICCWS and kCES device’s ...

Page 28

SHARP 6.2.4 AC CHARACTERISTICS - READ-ONLY OPERATIONS(l) tr, nv OE# to Outnut in Low Z I bHOZ ) OE# High to Output in High Z r Output Hold from Address, CE# or OE# Change, Whichever tOH Occurs First BYTE# to ...

Page 29

SHARI= Device Standby Address Selection VIH DDRESSES(A) VIL OE#(G) ::r WE#(W) l)----- VOH HIGH 2 DATA(D/Q) DQo-DQls) VOL tPHQV VIH RPMP Figure 11. AC Waveform for Read Operations LHF16Vll Data Valid ___________ Address Stable tAVAV _____--__-- ___________ -----------\ ...

Page 30

SHARP Device Standby Address Selection r VIH iDDRESSES \ VIL VIH CE#( VIH OE#(G) VlL tELN +....+ VIH BYTE#(F) VIL VOH DATA(D/Q) (DQs-DQls) VOL LHF16Vll Data Valid ___________ Address Stable -__-------- _____--_--_ , __._______. I tGLOV , tNGV ...

Page 31

SHARP 6.2.5 AC CHARACTERISTICS NOTES: 1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 4 ...

Page 32

SHARP VIH ADDRESSES(A) VIL VIH CE#(E) VU VIH OE#(G) VIH WE#(W) VIL VIH DATA(D/Q) VIH High Z RY/BY#(R) VOL VIH WP#(S) VU RP#(P) NOTES: 1. VCC power-up and standby. 2. Write block erase or word/byte write setup. 3. Write block ...

Page 33

SHARP 6.2.6 ALTERNATIVE CE#-CONTROLLED NOTES systems where CE# defines the write pulse width (within a longer WE# timing waveform), all setup, hold, and inactive WE# times should be measured relative to the CE# waveform. 2. Sampled, not 100% ...

Page 34

SliARP VIH ADDRESSES(A) VIL VIH CE#(E) VU VIH OEW) VU VIH WWW VU VIH DATA(D/Q) VIH BYTE#(F) RY/BY#(R) VIH WP#(S) VHH RPNP) VIH “PPW NOTES: 1. VCC power-up and standby. 2. Write block erase or word/byte write ...

Page 35

SHARP RESET OPERATIONS --a-- - RY/BY#(R) VOL VIH RwP) VIL High 2 RY/BY#(R) VOL VIH RwP) VIL 2.w vcc VIL VIH RP#(P) VIL Figure 15. AC Waveform for Reset Operation Parameter Sym. RP# Pulse Low Time tPLPH (If RP# tied ...

Page 36

SHARP 6.28 BLOCK ERASE AND WORD/BYTE Sym. Parameter twHQvl 32K word Block Word/Byte Write Time 4K word Block tEHOV1 32K word Block Block Write Time 4K word Block twHQv2 Block Erase Time 32K word Block 4K word Block tFHOV2 twHRzl ...

Page 37

... Card board ________________________________________----------------------------------------------------------------------------------------------------.---- Label Paper --_______--_____-_------------------------------------------------------------------------------------------------------------------------------------------- Outer case Card board (Devices shall be placed into a tray in the same direction.) LHFl6Vll LH28F160BVHE-BTL90 SHARP ww xxx Indicates the product was manufactured (Ol,OZ, 03, l Denotes the production year. (Lower two digit ’ Denotes the product ion ref .code (No marking , the country of origin ...

Page 38

StiARP 3-2. Outline dimension of tray Refer to attached drawing Storage and Opening of Dry Packing 4. 4-1. Store under conditions shown below before ( 1) Temperature range ( 2) Humidity 4-2. Notes on opening the dry packing (1) Before ...

Page 39

SHARP . rJAPANJ 4~&3%6~~~~-3~~~ Marking specification when “JAPAN” is marked. 434/ ‘/ - Fj&Jz 1 TIN-LEE NAME ! TSOP48-P-1220 LEAD FINISH 1 PLATING NOTE Plastic $42 I UNIT ) DRAWING NO, i AA1142 LHFlGVll DETAIL A -9 jZ’f~P~~~~-99#~fb, /?I &$&%(l)t-f7d ...

Page 40

SHARP LH28FlfiOBVHE-BTL90 - ZYYWW 19.0 DETAIL A DETAIL . pi ANJ ~%9$t~t\!$$&0~‘- NOTES : Marking specification when “JAPAN” is not marked. %wij !J - F4k-t j TIN-LEE ##% -9j~;f7’I1:s’r-‘j~~~L,/~9Q%dBlr\bnlr’r7d. NAME j TSOP48-P-1220 ...

Page 41

SHARF’ 43rj NAME:TSOP48-1220TCM- DRAWING NO. j CV756 UNIT j mm LHFlGVll t&5 NOTE ...

Page 42

... Mounting method Reflow soldering conditions Measurement point Storage conditions Note Recommended Reflow LHFlGVll LHFlGVll for two time reflow soldering LH28F160BVHE-BTL90 (TSOP48-P-1220) Tray (Dry packing) Reflow soldering (Air) Peak temperature of 230°C or less. 200°C or over, duration of less than 40 seconds. Preheat temperature of 125-15O” ...

Page 43

... Such noises, when induced onto WE# signal commands, causing undesired To protect the data stored in the flash memory against operating with the flash memory should have the following appropriate: 1) Protecting data in specific By setting a WP# to low, only the boot block Parameter and main blocks cannot be locked ...

Page 44

SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all ...

Related keywords