LH28F800SUT-70 Sharp Electronics, LH28F800SUT-70 Datasheet - Page 6

• Manufacturer Part Number: LH28F800SUT-70
• Manufacturer: Sharp Electronics

Specifications of LH28F800SUT-70

• Cell Type: NOR
• Density: 8Mb
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20/19Bit
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Program/erase Volt (typ): 4.5 to 5.5V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 3/4.5V
• Operating Supply Voltage (max): 3.6/5.5V
• Word Size: 8/16Bit
• Number Of Words: 1M/512K
• Supply Current: 35mA
• Mounting: Surface Mount
• Pin Count: 56
• Lead Free Status / Rohs Status: Not Compliant

LH28F800SU
1.2 mm thick × 14 mm × 20 mm TSOP (Type I) pack-
age. This form factor and pinout allow for very high board
layout densities.
tem interface between the microprocessor or
microcontroller and the internal memory operation.
Writes and Block Erase operations to be executed
using a Two-Write command sequence to the CUI in
the same way as the LH28F008SA 8M Flash memory.
basic LH28F008SA command-set to achieve higher
write performance and provide additional capabilities.
These new commands and features include:
• Page Buffer Writes to Flash
• Command Queuing Capability
• Automatic Data Writes During Erase
• Software Locking of Memory Blocks
• Two-Byte Successive Writes in 8-bit Systems
• Erase All Unlocked Blocks
word increments typically within 8 µs, a 25% improve-
ment over the LH28F008SA. A Block Erase operation
erases one of the 16 blocks in typically 0.7 seconds,
independent of the other blocks, which is about 55%
improvement over the LH28F008SA.
256 Bytes (128 Words) each to allow page data writes.
This feature can improve a system write performance
over previous flash memory devices.
commands to the device. Three Status Registers (de-
scribed in detail later) and a RY
information on the progress of the requested operation.
plete before the next operation can be requested, the
LH28F800SU allows queuing of the next operation while
the memory executes the current operation. This elimi-
nates system overhead when writing several bytes in a
row to the array or erasing several blocks at the same
time. The LH28F800SU can also perform write opera-
tions to one block of memory while performing erase of
another block.
locking to protect code or data such as Device Drivers,
PCMCIA card information, ROM-Executable O/S or Ap-
plication Code. Each block has an associated non-
volatile lock-bit which determines the lock status of the
block. In addition, the LH28F800SU has a master Write
Protect pin (WP
memory blocks whose lock-bits are set.
6
The LH28F800SU will be available in a 56-pin,
A Command User Interface (CUI) serves as the sys-
Internal Algorithm Automation allows Byte/Word
A Superset of commands have been added to the
Writing of memory data is performed in either byte or
The LH28F800SU incorporates two Page Buffers of
All operations are started by a sequence of Write
While the LH28F008SA requires an operation to com-
The LH28F800SU provides user-selectable block
»
) which prevents any modification to
»
/ BY
»
output pin provide
Registers to accomplish various functions:
•
•
•
Word-Wide modes are shown in Figures 5 and 6.
RY
tie many RY
figuration such as a Resident Flash Array.
able function with two input pins. CE
pins have exactly the same functionality as the regular
chip-enable pin CE
chip designs, CE
as the chip enable input. The LH28F800SU uses the
logical combination of these two signals to enable or
disable the entire chip. Both CE
tive low to enable the device and if either one
becomes inactive, the chip will be disabled. This fea-
ture, along with the open drain RY
system designer to reduce the number of control pins
used in a large array of 8M devices.
the LH28F800SU. BY
with address A
byte. On the other hand, BY
16-bit operation with address A
order address and address A
A block diagram is shown in Figure 3.
access time of each version, as follows:
TEMPERATURE
The LH28F800SU contains three types of Status
A Compatible Status Register (CSR) which is
100% compatible with the LH28F008SA Flash
memory’s Status Register. This register, when used
alone, provides a straightforward upgrade capabil-
ity to the LH28F800SU from a LH28F008SA
based design.
A Global Status Register (GSR) which informs the
system of command Queue status. Page Buffer sta-
tus, and overall Write State Machine (WSM) status.
16 Block Status Register (BSRs) which provide
block-specific status information such as the block
lock-bit status.
The GSR and BSR memory maps for Byte-Wide and
The LH28F800SU incorporates an open drain
The LH28F800SU also incorporates a dual chip-en-
The BY
The LH28F800SU is specified for a maximum
»
OPERATING
/ BY
0 - 70°C
0 - 70°C
0 - 70°C
0 - 70°C
»
output pin. This feature allows the user to OR-
»
T E
»
/ BY
»
pin allows either x8 or x16 read/writes to
8M (512K × 16, 1M × 8) Flash Memory
0
»
pins together in a multiple memory con-
»
selecting between low byte and high
1
may be tied to ground and use CE
»
on the LH28F008SA. For minimum
V
4.75 - 5.25 V
»
T E
4.5 - 5.5 V
3.0 - 3.6 V
2.7 - 3.6 V
CC
»
at logic low selects 8-bit mode
SUPPLY
»
T E
0
is not used (don’t care).
»
0
1
»
at logic high enables
and CE
becoming the lowest
»
/ BY
»
0
and CE
MAX. ACCESS
»
pin, allows the
»
1
120 ns
160 ns
(T
must be ac-
70 ns
80 ns
ACC
»
1
. These
)
»
0