LH28F800SUT-70 Sharp Electronics, LH28F800SUT-70 Datasheet

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LH28F800SUT-70

Manufacturer Part Number
LH28F800SUT-70
Description
Manufacturer
Sharp Electronics
Datasheet

Specifications of LH28F800SUT-70

Cell Type
NOR
Density
8Mb
Interface Type
Parallel
Boot Type
Not Required
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
0C to 70C
Package Type
TSOP-I
Program/erase Volt (typ)
4.5 to 5.5V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
3/4.5V
Operating Supply Voltage (max)
3.6/5.5V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
35mA
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant

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LH28F800SUT-70
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Part Number:
LH28F800SUT-70
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SHARP
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5 380
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LH28F800SUT-70
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Part Number:
LH28F800SUT-70
Manufacturer:
SHARP
Quantity:
1 000
Part Number:
LH28F800SUT-70
Manufacturer:
SHARP
Quantity:
20 000
LH28F800SU
FEATURES
User-Configurable x8 or x16 Operation
User-Selectable 3.3 V or 5 V V
5 V Write/Erase Operations (5 V V
– No Requirement for DC/DC
70 ns Maximum Access Time
Minimum 2.7 V Read capability
– 160 ns Maximum Access Time
16 Independently Lockable Blocks
0.32 MB/sec Write Transfer Rate
100,000 Erase Cycles per Block
Revolutionary Architecture
– Pipelined Command Execution
– Write During Erase
– Command Superset of
5 µA (TYP.) I
1 µA (TYP .) Deep Power-Down
State-of-the-Art 0.55 µm ETOX™
Flash Technology
56-Pin, 1.2 mm × 14 mm × 20 mm
TSOP (Type I) Package
Converter to Write/Erase
(V
Sharp LH28F008SA
CC
= 2.7 V)
CC
in CMOS Standby
CC
PP
)
56-PIN TSOP
Figure 1. TSOP Reverse Bend Configuration
RY/BY
BYTE
DQ
DQ
DQ
DQ
DQ
GND
GND
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
V
V
WP
WE
8M (512K × 16, 1M × 8) Flash Memory
OE
NC
NC
CC
CC
A
15
14
13
12
10
11
7
6
5
4
3
2
9
1
8
0
0
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
10
12
13
14
15
16
17
18
19
20
22
23
24
25
26
27
28
11
21
1
2
3
4
5
6
7
8
9
TOP VIEW
28F800SUR-1
CE
RP
3/5
CE
NC
NC
A
A
A
A
V
A
A
A
A
V
A
A
A
A
GND
A
A
A
A
A
A
A
19
18
17
16
CC
15
14
13
12
PP
11
10
9
8
7
6
5
4
3
2
1
0
1
1

Related parts for LH28F800SUT-70

LH28F800SUT-70 Summary of contents

Page 1

... Write During Erase – Command Superset of Sharp LH28F008SA • 5 µA (TYP CMOS Standby CC • 1 µA (TYP .) Deep Power-Down • State-of-the-Art 0.55 µm ETOX™ Flash Technology • 56-Pin, 1.2 mm × × TSOP (Type I) Package 8M (512K × 16, 1M × 8) Flash Memory 56-PIN TSOP RY/ ...

Page 2

... GND 48 tecture (100% compatible with the LH28F008SA Flash memory, the LH28F016SA 16M Flash memory and the LH28F016SU 16M 5 V single voltage Flash memory), extended cycling, low power 3.3 V operation very fast write and read performance and selective block 4 V locking provide a highly flexible memory component suit- ...

Page 3

... Flash Memory OUTPUT BUFFER OUTPUT MULTIPLEXER INPUT BUFFER Y-DECODER ADDRESS X-DECODER QUEUE LATCHES ADDRESS COUNTER Figure 3. LH28F800SU Block Diagram (Architectural Evolution Includes Page Buffers, Queue Registers and Extended Status Registers OUTPUT INPUT BUFFER BUFFER DATA ID QUEUE REGISTER ...

Page 4

... When returning from » is high. » » » overrides OE , and OE overrides WE. X » 8M (512K × 16, 1M × 8) Flash Memory - A selects 6 15 » high, the device is de-selected and power 1 » » disables the device. ...

Page 5

... Flash Memory PIN DESCRIPTION (Continued) SYMBOL TYPE WRITE PROTECT: Erase blocks can be locked by writing a non-volatile lock-bit for each block. When WP is low, those locked blocks as reflected by the Block-Lock Status WP INPUT bits (BSR.6), are protected from inadvertent Data Writes or Erases. When WP is high, all blocks can be Written or Erased regardless of the state of the lock-bits ...

Page 6

... The LH28F800SU is specified for a maximum access time of each version, as follows: OPERATING TEMPERATURE 0 - 70° 70° 70° 70°C 8M (512K × 16, 1M × 8) Flash Memory     »     » pins together in a multiple memory con-     »     » and CE ...

Page 7

... Flash Memory The LH28F800SU incorporates an Automatic Power Saving (APS) feature which substantially reduces the active current when the device is in static mode of operation (addresses not switching). In APS mode, the typical I current 5 3.3 V). A Deep Power-Down mode of operation is invoked   ...

Page 8

... RESERVED 00005H GSR 00004H RESERVED 00003H BSR0 00002H RESERVED 00001H RESERVED 00000H Figure 5. Extended Status Register Memory Map (Byte-Wide Mode (512K × 16, 1M × 8) Flash Memory x16 MODE RESERVED GSR RESERVED BSR15 RESERVED RESERVED . . . RESERVED RESERVED GSR RESERVED BSR0 RESERVED ...

Page 9

... Flash Memory BUS OPERATIONS, COMMANDS AND STATUS REGISTER DEFINITIONS Bus Operations for Word-Wide Mode (BY » » MODE Read Output Disable Standby Deep Power-Down Manufacturer Device Write Bus Operations For Byte-Wide Mode (BY » » MODE Read Output Disable ...

Page 10

... Write X FFH Write X 90H Write X 70H Write X 50H Write X 40H Write X 10H Write X 20H Write X B0H 8M (512K × 16, 1M × 8) Flash Memory SECOND BUS CYCLE NOTE OPER. ADDRESS DATA Read AA AD Read IA ID Read X CSRD Write WA WD Write WA WD Write BA D0H ...

Page 11

... Flash Memory LH28F800SU Performance Enhancement Command Bus Definitions FIRST BUS CYCLE COMMAND MODE OPER. ADDR. Read Extended Write Status Register Page Buffer Swap Write Read Page Buffer Write Single Load to Write Page Buffer x8 Write Sequential Load to Page Buffer ...

Page 12

... These commands reconfigure Write address, WA, is the Destination address in the flash array which must match the Source address in the Page Buffer. Refer to the LH28F800SU User’s Manual. 10. BCL = 00H corresponds to a Byte count of 1. Similarly, WCL = 00H corresponds to a Word count of 1. ...

Page 13

... Flash Memory GLOBAL STATUS REGISTER WSMS OSS DOS 7 6 GSR.7 = WRITE STATE MACHINE STATUS (WSMS Ready 0 = Busy GSR.6 = OPERATION SUSPEND STATUS (OSS Operation Suspended 0 = Operation in Progress/Completed GSR.5 = DEVICE OPERATION STATUS (DOS Operation Unsuccessful 0 = Operation Successful or Currently Running GSR ...

Page 14

... BSRs. 5. When multiple operations are queued, checking BSR.7 only provides indication of completion for that particular block. GSR.7 provides indication when all queued opera- tions are completed. 8M (512K × 16, 1M × 8) Flash Memory VPPS ...

Page 15

... Flash Memory ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings* Temperature under bias ......................... 0°C to +80°C Storage temperature ......................... -65°C to +125° 3.3 V ± 0.3 V Systems CC SYMBOL PARAMETER T Operating Temperature, Commercial with Respect to GND Supply Voltage with Respect to GND PP PP Voltage on any Pin (Except V ...

Page 16

... C IN Address/Control Pin C Capacitance Looking into an Output Pin OUT Load Capacitance Driven by Outputs for C LOAD Timing Specifications Equivalent Testing Load Circuit V Equivalent Testing Load Circuit V NOTE: 1. Sampled, not 100% tested (512K × 16, 1M × 8) Flash Memory TYP. MAX. UNITS 2.5 ns TYP. ...

Page 17

... Flash Memory Timing Nomenclature All 3.3 V systems are measured from where signals cross 1.5 V. For 5.0 V systems use the standard JEDEC cross point definitions. Each timing parameter consists of 5 characters. Some common examples are defined below:     » ...

Page 18

... OUTPUT FROM OUTPUT UNDER TEST 28F800SUR-7 Figure 10. Transient Equivalent Testing = 3.3 V) FROM OUTPUT UNDER TEST Figure 11. High Speed Transient Equivalent Testing Load Circuit (V 8M (512K × 16, 1M × 8) Flash Memory 2 TRANSMISSION LINE TEST POINT TOTAL CAPACITANCE = 50 pF 28F800SUR-8 Load Circuit ( ...

Page 19

... Flash Memory DC Characteristics V = 3.3 V ± 0 0°C to +70°C CC     » 3/5 = Pin Set High for 3.3 V Operations SYMBOL PARAMETER I Input Load Current IL I Output Leakage Current Standby Current CCS CC V Deep Power-Down CC I CCD Current ...

Page 20

... 0 0.0 5.5 V 5.0 4.5 5 25°C. These currents are valid for all less than Static operation. CCR (512K × 16, 1M × 8) Flash Memory TEST CONDITIONS NOTE V > Word/Byte PP PPH Write in Progress PPH Block Erase in Progress PPH Block Erase Suspended ...

Page 21

... Flash Memory DC Characteristics V = 5.0 V ± 0 0°C to +70°     » 3/5 Pin Set Low for 5 V Operations SYMBOL PARAMETER I Input Load Current IL I Output Leakage Current Standby Current CCS CC V Deep Power-Down CC I CCD Current ...

Page 22

... 0 0.0 5.5 V 5.0 4.5 5 25°C. These currents are valid for all less than Static operation. CCR (512K × 16, 1M × 8) Flash Memory TEST CONDITIONS NOTE V > Word/Byte PP PPH Write in Progress PPH Block Erase in Progress PPH Block Erase Suspended ...

Page 23

... Flash Memory AC Characteristics - Read Only Operations T = 0°C to +70°C A SYMBOL PARAMETER t Read Cycle Time AVAV t Address Setup to CE » Going Low AVEL » t Address Setup to OE Going Low AVGL t Address to Output Delay AVQV t CE » to Output Delay ELQV » ...

Page 24

... This timing parameter is used to latch the correct BSR data onto the outputs (Continued 5.0 V ± 0.25V V CC MIN. MAX 400 »     » after the falling edge of CE without impact (512K × 16, 1M × 8) Flash Memory = 5.0 V ± 0.5V CC UNITS NOTE MIN. MAX 480 ...

Page 25

... Flash Memory V POWER-UP STANDBY ADDRESSES ( ( (NOTE ( ( HIGH-Z OH DATA (D/ 5 GND ( NOTE defined as the latter DEVICE AND ADDRESS SELECTION OUTPUTS ENABLED ADDRESSES STABLE t AVAV t AVEL t AVGL t GLQV t ELQV t GLQX t ELQX t AVQV t PHQV or CE going LOW or the first of CE ...

Page 26

... FLQV t GLQV t ELQV t GLQX t ELQX t AVQV t FLQZ or CE going LOW or the first     »     » Figure 13 Timing Waveforms 8M (512K × 16, 1M × 8) Flash Memory . . . . . . . . . t EHQZ . . . t GHQZ = t AVQV . . . HIGH-Z DATA DATA OUTPUT OUTPUT . . . HIGH-Z DATA OUTPUT going HIGH. 1 28F800SUR-11 ...

Page 27

... Flash Memory RP (P) ADDRESS (A) DATA (Q) RP (P) 3/5 ( ADDRESS (A) DATA (Q) Figure 14 PLPH t AVQV t PHQV t PLPH t YHPH t PLYL 3.3 V 4 3VPH PL5V VALID t AVQV VALID t PHQV     » Power-Up and RP Reset Waveforms CC LH28F800SU VALID VALID t YLPH 5.0 V ...

Page 28

... High = 5 V ± 10 ± 10% CC times. PHQV     » going Low. RP     » is required to stay low, until V operation. Refer to the AC Characteristics Read Only CC 8M (512K × 16, 1M × 8) Flash Memory MIN. MAX. UNIT NOTE 0 µs 2 µs 0 µs 100 ns 100 ...

Page 29

... Flash Memory AC Characteristics for WE     » - Controlled Command Write Operations T = 0°C to +70°C A SYMBOL PARAMETER t Write Cycle Time AVAV t V Setup to WE Going High VPWH PP t » » RP Setup to CE Going Low PHEL t » CE Setup to WE Going Low ...

Page 30

... BY High » » High 8 4.5 0.3     »     » going High     » for all Command Write Operations. 8M (512K × 16, 1M × 8) Flash Memory 1 (Continued 5.0 ± 0 UNITS NOTE TYP. MIN. MAX 100 ns 3 480 ...

Page 31

... Flash Memory WRITE DATA-WRITE OR ERASE DEEP SETUP COMMAND POWER-DOWN V ADDRESSES (A) IH (NOTE AVAV V ADDRESSES (A) IH (NOTE AVAV CE ( (NOTE WHEH t ELWL ( ( WLWH V HIGH-Z IH DATA (D/ PHWL V OH RY/ PPH V ( PPL NOTES: 1. This address string depicts Data-Write/Erase cycles with corresponding verification via ESRD. ...

Page 32

... Duration of Word/Byte Write Operation EHQV 2 t Duration of Block Erase Operation EHQV 3.3 V ±0 TYP. MIN. 120 480 100 » » High » Going Low » » High 12 5 0.3 8M (512K × 16, 1M × 8) Flash Memory 1 UNITS NOTE MAX 100 µs ns µs µ ...

Page 33

... Flash Memory AC Characteristics for CE     » - Controlled Command Write Operations T = 0°C to +70°C A SYMBOL PARAMETER t Write Cycle Time AVAV » Setup to WE Going Low PHWL » Setup to CE Going High VPEH Setup to CE » Going Low WLEL » ...

Page 34

... AVEH EHAX t t EHEL EHQV1 EHDX t DVEH EHRL t VPEH going LOW or the first going HIGH (512K × 16, 1M × 8) Flash Memory READ EXTENDED STATUS REGISTER DATA READ COMPATIBLE STATUS REGISTER DATA t EHGL t GHEL OUT IN t RHPL (NOTE 5) t QVVL 28F800SUR-14 ...

Page 35

... Flash Memory AC Characteristics for Page Buffer Write Operations T = 0°C to +70°C A SYMBOL PARAMETER t Write Cycle Time AVAV t CE » Setup to WE Going Low ELWL t Address Setup to WE Going Low AVWL t Data Setup to WE Going High DVWH ...

Page 36

... TYP. MIN. MAX. UNITS 8 0.54 2.1 0.27 1.0 0.7 10 11.2 8M (512K × 16, 1M × 8) Flash Memory t WHWL t WHAX 28F800SUR-15 TEST CONDITIONS µs s Byte Write Mode s Word Write Mode s s TEST CONDITIONS µs s Byte Write Mode s Word Write Mode ...

Page 37

... MAXIMUM LIMIT DIMENSIONS IN MM [INCHES] MINIMUM LIMIT ORDERING INFORMATION LH28F800SU T Device Type Package Speed Example: LH28F800SUT-70 (8M (512K x 16 Flash Memory, 70 ns, 56-pin TSOP 0.13 [0.005] 20.30 [0.799] 19.70 [0.776] 18.60 [0.732] 18.20 [0.717] 19.30 [0.760] 18.70 [0.736] -## 70 Access Time (ns) 56-pin, 1 ...

Page 38

... Telex: 49608472 (SHARPCAM) Facsimile: (360) 834-8903 http://www.sharpmeg.com ©1997 by SHARP Corporation Issued May 1996 8M (512K × 16, 1M × 8) Flash Memory EUROPE SHARP Electronics (Europe) GmbH Microelectronics Division Sonninstraße 3 20097 Hamburg, Germany Phone: (49) 40 2376-2286 Telex: 2161867 (HEEG D) Facsimile: (49) 40 2376-2232 ...

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