LH28F800SUT-70 Sharp Electronics, LH28F800SUT-70 Datasheet - Page 4
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LH28F800SUT-70
Manufacturer Part Number
LH28F800SUT-70
Description
Manufacturer
Sharp Electronics
Datasheet
1.LH28F800SUT-70.pdf
(38 pages)
Specifications of LH28F800SUT-70
Cell Type
NOR
Density
8Mb
Interface Type
Parallel
Boot Type
Not Required
Address Bus
20/19Bit
Operating Supply Voltage (typ)
3.3/5V
Operating Temp Range
0C to 70C
Package Type
TSOP-I
Program/erase Volt (typ)
4.5 to 5.5V
Sync/async
Asynchronous
Operating Temperature Classification
Commercial
Operating Supply Voltage (min)
3/4.5V
Operating Supply Voltage (max)
3.6/5.5V
Word Size
8/16Bit
Number Of Words
1M/512K
Supply Current
35mA
Mounting
Surface Mount
Pin Count
56
Lead Free Status / Rohs Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH28F800SUT-70
Manufacturer:
SHARP
Quantity:
5 380
Company:
Part Number:
LH28F800SUT-70
Manufacturer:
SHARP
Quantity:
5 380
Company:
Part Number:
LH28F800SUT-70
Manufacturer:
SHARP
Quantity:
23 511
Part Number:
LH28F800SUT-70
Manufacturer:
SHARP
Quantity:
20 000
LH28F800SU
PIN DESCRIPTION
4
DQ
CE
DQ
SYMBOL
A
A
RY
16
1
8
»
0
0
WE
RP
OE
, CE
A
- A
- DQ
- A
- DQ
»
/ BY
0
»
»
15
19
»
1
»
15
7
INPUT
INPUT
INPUT
INPUT/OUTPUT
INPUT/OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN DRAIN
OUTPUT
TYPE
BYTE-SELECT ADDRESS: Selects between high and low byte when device is in x8
mode. This address is latched in x8 Data Writes. Not used in x16 mode (i.e., the
WORD-SELECT ADDRESSES: Select a word within one 64K block. A
1 of 1024 rows, and A
latched during Data Writes.
BLOCK-SELECT ADDRESSES: Select 1 of 16 Erase blocks. These addresses are
latched during Data Writes, Erase and Lock-Block operations.
LOW-BYTE DATA BUS: Inputs data and commands during CUI write cycles.
Outputs array, buffer, identifier or status data in the appropriate Read mode. Floated
when the chip is de-selected or the outputs are disabled.
HIGH-BYTE DATA BUS : Inputs data during x16 Data-Write operations. Outputs
array, buffer or identifier data in the appropriate Read mode; not used for Status
register reads. Floated when the chip is de-selected or the outputs are disabled.
CHIP ENABLE INPUTS : Activate the device’s control logic, input buffers, decoders and
sense amplifiers. With either CE
consumption reduces to Standby levels upon completion of any current Data-Write or
Erase operations. Both CE
specifications are the same for both signals. Device Selection occurs with the latter
falling edge of CE
RESET/POWER-DOWN: With RP
aborted and device is put into the deep power down mode. When the power is turned
on, RP
the 3/5
RP
Deep Power-Down, a recovery time of 400 ns (V
these circuits to power-up. When RP
operation(s) are terminated, and the device is reset. All Status registers return to ready
(with all status flags cleared). After returning, the device is in read array mode.
OUTPUT ENABLE: Gates device data through the output buffers when low. The
outputs float to tri-state off when OE
NOTE: CE
WRITE ENABLE: Controls access to the CUI, Page Buffers, Data Queue Registers
and Address Queue Latches. WE is active low, and latches both address and data
(command or array) on its rising edge.
READY/BUSY: Indicates status of the internal WSM. When low, it indicates that the
WSM is busy performing an operation. RY
for new operations (or WSM has completed all pending operations), or Erase is
Suspended, or the device is in deep power-down mode. This output is always active
(i.e., not floated to tri-state off when OE
Pin Disable command is issued.
A
0
»
input buffer is turned off when BYTE is high).
is required to stay low in order to protect data from noise. When returning from
»
»
pin is switched, or when the power transition is occurred, or at the power on/off,
pin is turned to low in order to return the device to default configuration. When
»
X
overrides OE
»
0
or CE
1
- A
»
1
»
, and OE
. The first rising edge of CE
5
selects 16 of 512 columns. These addresses are
»
0
, CE
NAME AND FUNCTION
»
0
»
or CE
low, the device is reset, any current operation is
»
»
1
overrides WE.
»
is high.
must be low to select the device. All timing
»
or CE
»
1
»
goes low, any current or pending WSM
»
/ BY
high, the device is de-selected and power
8M (512K × 16, 1M × 8) Flash Memory
»
»
0
high indicates that the WSM is ready
CC
, CE
+5.0 V ±0.25 V) is required to allow
»
1
are high), except if a RY
»
0
or CE
»
1
disables the device.
6
- A
15
selects
»
/ BY
»