AM29LV800DT-70EC AMD (ADVANCED MICRO DEVICES), AM29LV800DT-70EC Datasheet - Page 24

• Manufacturer Part Number: AM29LV800DT-70EC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29LV800DT-70EC

• Lead Free Status / Rohs Status: Not Compliant

8.6
8.7
24
Chip Erase Command Sequence
Sector Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the chip erase
command, which in turn invokes the Embedded Erase algorithm. The device does not require the system to
preprogram prior to erase. The Embedded Erase algorithm automatically preprograms and verifies the entire
memory for an all zero data pattern prior to electrical erase. The system is not required to provide any
controls or timings during these operations.
for the chip erase command sequence.
Any commands written to the chip during the Embedded Erase algorithm are ignored. Note that a hardware
reset during the chip erase operation immediately terminates the operation. The Chip Erase command
sequence should be reinitiated once the device returns to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See
Operation Status on page 27
complete, the device returns to reading array data and addresses are no longer latched.
Figure 8.2 on page 25
on page 39
Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector erase command.
and data requirements for the sector erase command sequence.
The device does not require the system to preprogram the memory prior to erase. The Embedded Erase
algorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase.
The system is not required to provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase commands may be written. Loading the sector erase buffer may
be done in any sequence, and the number of sectors may be from one sector to all sectors. The time between
these additional cycles must be less than 50 µs, otherwise the last address and command might not be
accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to
ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is
written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the
system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the
time-out period resets the device to reading array data. The system must rewrite the command sequence
and any additional sector addresses and commands.
The system can monitor DQ3 to determine if the sector erase timer has timed out. (See
Timer on page
sequence.
Once the sector erase operation begins, only the Erase Suspend command is valid. All other commands are
ignored. Note that a hardware reset during the sector erase operation immediately terminates the operation.
The Sector Erase command sequence should be reinitiated once the device returns to reading array data, to
ensure data integrity.
When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses
are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2,
or RY/BY#. Refer to
Figure 8.2 on page 25
on page 39
for parameters, and
for parameters, and to
30.) The time-out begins from the rising edge of the final WE# pulse in the command
Write Operation Status on page 27
illustrates the algorithm for the erase operation. See
illustrates the algorithm for the erase operation. Refer to
for information on these status bits. When the Embedded Erase algorithm is
Figure 15.6 on page 40
Figure 15.6 on page 40
S29AL008D
Table 8.1 on page 26
D a t a
S h e e t
for information on these status bits.
for timing diagrams.
for timing diagrams.
shows the address and data requirements
Table 8.1 on page 26
S29AL008D_00_A11 February 27, 2009
Erase/Program Operations
Erase/Program Operations
DQ3: Sector Erase
shows the address
Write