AM29LV800DT-70EC AMD (ADVANCED MICRO DEVICES), AM29LV800DT-70EC Datasheet
AM29LV800DT-70EC
Specifications of AM29LV800DT-70EC
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AM29LV800DT-70EC Summary of contents
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... S29AL008D 8 Megabit (1M x 8-Bit/512 K x 16-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory Data Sheet This product has been retired and is not recommended for designs. For new and current designs, S29AL008J supercedes S29AL008D. This is the factory-recommended migration path. Please refer to the S29AL008J data sheet for specifications and ordering information ...
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Notice On Data Sheet Designations Spansion Inc. issues data sheets with Advance Information or Preliminary designations to advise readers of product information or intended specifications throughout the product life cycle, including development, qualification, initial production, and full production. In all ...
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... Embedded Program algorithm automatically writes and verifies data at specified addresses Compatibility with JEDEC Standards – Pinout and software compatible with single-power supply Flash – Superior inadvertent write protection Publication Number S29AL008D_00 Performance Characteristics High Performance – ...
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... General Description The S29AL008D Mbit, 3.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. For more information, refer to publication number 21536. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7– ...
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... DQ5: Exceeded Timing Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 9.7 DQ3: Sector Erase Timer 10. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 11. Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 12. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 12.1 Zero Power Flash 13. Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 14. Key to Switching Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 15. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15.1 Erase/Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 15.2 Erase and Programming Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 16. Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 ...
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TS 048—48-Pin Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figures Figure 3.1 Standard TSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Tables Table 7.1 S29AL008D Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Product Selector Guide Full Voltage Range: V Speed Options Regulated Voltage Range: V Max access time ACC Max CE# access time Max OE# access time Note See AC Characteristics on page 36 2. ...
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Connection Diagrams A15 1 A14 2 A13 3 4 A12 A11 5 A10 WE# RESET RY/BY# 15 A18 16 A17 ...
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... Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time ...
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Pin Configuration I/O Name A0–A18 DQ0–DQ14 DQ15/A-1 BYTE# CE# OE# WE# RESET# RY/BY Logic Symbol Description 19 addresses 15 data inputs/outputs DQ15 (data ...
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... M = Small Outline Package (SOP) Standard Pinout Speed Option Access Speed Access Speed Access Speed Access Speed Device Number/Description S29AL008D 8 Megabit Flash Memory manufactured using 200 nm process technology 3.0 Volt-only Read, Program, and Erase S29AL008D Valid Combinations Package Type, Speed Material, and Model Option ...
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Device Bus Operations This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory location. The register is composed of ...
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... DC Characteristics on page 7.6 Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I ...
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... CMOS standby current (I greater. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firmware from the Flash memory. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains a 0 (busy) until the internal reset operation is complete, which requires a time of t system can thus monitor RY/BY# to determine whether the reset operation is complete ...
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Sector A18 A17 SA0 0 0 SA1 0 0 SA2 0 0 SA3 0 0 SA4 0 0 SA5 0 0 SA6 0 0 SA7 0 1 SA8 0 1 SA9 0 1 SA10 0 1 SA11 1 0 SA12 ...
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... The alternate method intended only for programming equipment requires V This method is compatible with programmer routines written for earlier 3.0 volt-only Spansion flash devices. Publication number 20536 contains further details; contact an Spansion representative to request a copy. ...
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Temporary Sector Unprotect This feature allows temporary unprotection of previously protected sectors to change data in-system. The Sector Unprotect mode is activated by setting the RESET# pin to V sectors can be programmed or erased by selecting the sector ...
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Figure 7.2 In-System Sector Protect/Sector Unprotect Algorithms START PLSCNT = 1 RESET Wait First Write Temporary Sector Cycle = 60h? Unprotect Mode Yes Set up sector address Sector Protect: Write 60h to sector address ...
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Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system ...
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Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence ...
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Unlock Bypass Command Sequence The unlock bypass feature allows the system to program bytes or words to the device faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock ...
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Chip Erase Command Sequence Chip erase is a six bus cycle operation. The chip erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two additional unlock write cycles are then followed by the ...
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Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the ...
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Command Sequence (Note 1) Read (Note 6) 1 Reset (Note 7) 1 Word Manufacturer ID 4 Byte Word Device ID, 4 Top Boot Block Byte Word Device ID, 4 Bottom Boot Block Byte Word Sector Protect Verify 4 (Note 9) ...
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Write Operation Status The device provides several bits to determine the status of a write operation: DQ2, DQ3, DQ5, DQ6, DQ7, and RY/BY#. Table 9.1 on page 31 RY/BY#, and DQ6 each offer a method for determining whether a ...
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Notes Valid address for programming. During a sector erase operation, a valid address is an address within any sector selected for erasure. During chip erase, a valid address is any non-protected sector address. 2. DQ7 should be ...
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During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After ...
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DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a 1. This is a failure condition that indicates the program or erase cycle was ...
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After the sector erase command sequence is written, the system should read the status on DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure the device accepted the command sequence, and then read DQ3. If DQ3 is 1, the ...
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Operating Ranges Industrial (I) Devices Ambient Temperature (T Extended (N) Devices Ambient Temperature (T V Supply Voltages CC V for regulated voltage range+3 +3 for full voltage range CC Operating ranges define those limits ...
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DC Characteristics Parameter I Input Load Current Input Load Current LIT I Output Leakage Current LO V Active Read Current CC I CC1 (Notes Active Write Current CC I CC2 (Notes 2, 3, ...
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... Zero Power Flash Figure 12.1 I CC1 500 1000 Note Addresses are switching at 1 MHz Note ° Current vs. Time (Showing Active and Automatic Sleep Currents) 1500 2000 2500 Time in ns Figure 12.2 Typical I vs. Frequency CC1 2 3 Frequency in MHz S29AL008D 3000 ...
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Test Conditions Device Under Test Note Nodes are IN3064 or equivalent. Output Load Output Load Capacitance, C (including jig capacitance) Input Rise and Fall Times Input Pulse Levels Input timing measurement reference levels Output timing measurement reference levels 14. ...
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AC Characteristics Parameter JEDEC Std t t Read Cycle Time (Note 1) AVAV Address to Output Delay AVQV ACC t t Chip Enable to Output Delay ELQV Output Enable to Output Delay GLQV ...
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Parameter JEDEC Std RESET# Pin Low (During Embedded Algorithms READY Read or Write RESET# Pin Low (NOT During Embedded t READY Algorithms) to Read or Write t RESET# Pulse Width RP t RESET# High Time Before Read RH ...
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Parameter JEDEC Std t t ELFL/ ELFH t FLQZ t FHQV BYTE# DQ0–DQ14 Switching from word to byte mode DQ15/A-1 BYTE# Switching from byte to DQ0–DQ14 word mode DQ15/A-1 CE# WE# BYTE# Note Refer to Erase/Program Operations on page 39 ...
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Erase/Program Operations Parameter JEDEC Std t t Write Cycle Time AVAV Address Setup Time AVWL Address Hold Time WLAX Data Setup Time DVWH Data Hold Time WHDX ...
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Addresses CE# OE# WE# Data RY/BY# t VCS V CC Notes sector address (for Sector Erase Valid Address for reading status data (see 2. Illustration shows device in word mode. Addresses CE# OE# WE# Data ...
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Addresses CE OE# WE# DQ7 DQ0–DQ6 t BUS RY/BY# Note VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data read cycle Addresses CE OE# WE# DQ6/DQ2 ...
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Enter Erase Embedded Suspend Erasing Erase Erase Suspend WE# DQ6 DQ2 Note The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an erase-suspended sector. Parameter JEDEC Std t ...
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Figure 15.12 Sector Protect/Unprotect Timing Diagram RESET# SA, A6, A1, A0 Sector Protect/Unprotect Data 60h 1 µs CE# WE# OE# Note For sector protect For sector unprotect, ...
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Addresses WE# OE# CE# Data t RH RESET# RY/BY# Notes program address program data, DQ7# = complement of the data written to the device Figure indicates the last two bus cycles of command ...
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Input voltage with respect to V (including A9, OE#, and RESET#) Input voltage with respect Current CC Note Includes all pins except V CC Parameter Symbol OUT C IN2 Notes 1. Sampled, not 100% ...
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Physical Dimensions 16.1 TS 048—48-Pin Standard TSOP PACKAGE JEDEC SYMBOL MIN A --- A1 0.05 A2 0.95 b1 0.17 b 0.17 c1 0.10 c 0.10 D 19.80 D1 18.30 E 11. 0.50 Θ 0˚ R 0.08 N ...
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VBK 048—48 Ball Fine-Pitch Ball Grid Array (FBGA) 8.15 x 6.15 mm INDEX MARK PIN A1 CORNER PACKAGE VBK 048 JEDEC N/A 6. 8.15 mm NOM PACKAGE SYMBOL MIN NOM A --- --- A1 ...
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SO 044—44-Pin Small Outline Package S29AL008D S29AL008D_00_A11 February 27, 2009 Dwg rev AC; 10/99 ...
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Revision History 17.1 Revision A (September 8, 2004) Initial release 17.2 Revision A 1 (February 18, 2005) Global Updated Trademark Ordering Information Added Package type designator Valid Combinations Changed Package Type, Material, and Temperature Range designator Under Package Descriptions, ...
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Revision A3 (June 16, 2005) Changed from Preliminary to full Data Sheet. Updated Valid Combinations table. 17.5 Revision A4 (February 16, 2006) Corrected minor typo on page 1. Added cover page. 17.6 Revision A5 (May 22, 2006) AC Characteristics ...
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Revision A10 (November 27, 2007) Figure: Input Waveforms and Measurement Levels Updated figure 17.12 Revision A11 (February 27, 2009) Global Added obsolescence information to Cover Sheet, Distinctive Characteristics, and Ordering Information sections of data sheet. February 27, 2009 S29AL008D_00_A11 ...
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Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated ...