IDTQS5LV919-133Q IDT, Integrated Device Technology Inc, IDTQS5LV919-133Q Datasheet
IDTQS5LV919-133Q
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IDTQS5LV919-133Q Summary of contents
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FEATURES: • 3.3V operation • JEDEC compatible LVTTL level outputs • Clock inputs are 5V tolerant • < 300ps output skew, Q – • 2xQ output, ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN CONFIGURATION GND OE/RST FEEDBACK 5 REF_SEL 6 SYNC AGND SYNC 11 ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PIN DESCRIPTION Pin Name I/O Description SYNC I Reference clock input 0 SYNC I Reference clock input 1 REF_SEL I Reference clock select. When 1, selects SYNC FREQ_SEL ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER FREQUENCY SELECTION TABLE Output Used for FREQ_SEL Feedback Min. HIGH Q/2 F MIN_Q/2 HIGH MIN_Q HIGH MIN_Q (3) HIGH 2xQ ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER INPUT TIMING REQUIREMENTS Symbol Description ( Maximum input rise and fall times, 0. Input Clock Frequency, SYNC I t Input ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER μ μ 0.1 F Low High Freq. Freq. Bypass Bypass Figure 1. Recommended Analog Isolation Scheme for the QS5LV919 NOTES: 1. Figure 1 shows an analog ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER PLL OPERATION The Phase Locked Loop (PLL) circuit included in the QS5LV919 provides for replication of incoming SYNC clock signals. Any manipulation of that signal, such as frequency ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER The frequency relationship shown here is applicable to all Q outputs (Q0, Q1, Q2, Q3 and Q4). 2:1 INPUT TO "Q" OUTPUT FREQUENCY RELATIONSHIP In this application, the ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER CLOCK @ f SYSTEM CLOCK SOUR CE DISTRIBUTE CLOCK @ f CLOCK @ 2f at point of use Figure 3. Multiprocessing Application Using the QS5LV919 for Frequency Multiplication ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER AC TEST LOADS AND WAVEFORMS OUTPUT 30pF TEST CIRCUIT 1 3. 0.8V 0V LVTTL INPUT TEST WAVEFORM CONTROL INPU T OUTPUT NOR ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER AC TIMING DIAGRAM SYNC FEEDBACK 2xQ t SKA NOTES Timing Diagram applies to Q output connected ...
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QS5LV919 3.3V LOW SKEW CMOS PLL CLOCK DRIVER WITH INTEGRATED LOOP FILTER ORDERING INFORMATION QS XXXX XX Device Type Speed CORPORATE HEADQUARTERS 6024 Silver Creek Valley Road San Jose, CA 95138 X X Package Process Blank ...