M29W640FT70N6E Micron Technology Inc, M29W640FT70N6E Datasheet - Page 24

• Manufacturer Part Number: M29W640FT70N6E
• Manufacturer: Micron Technology Inc

Specifications of M29W640FT70N6E

• Cell Type: NOR
• Density: 64Mb
• Access Time (max): 70ns
• Interface Type: Parallel
• Boot Type: Top
• Address Bus: 23/22Bit
• Operating Supply Voltage (typ): 3/3.3V
• Operating Temp Range: -40C to 85C
• Package Type: TSOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8/16Bit
• Number Of Words: 8M/4M
• Supply Current: 10mA
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / Rohs Status: Compliant

4.2.3
4.2.4
2. For devices with process technology code “H” in the marking, the Double Word Program command can be performed
24/71
without applying V
Octuple Byte Program command
This is used to write eight adjacent Bytes, in x8 mode, simultaneously. The addresses of the
eight Bytes must differ only in A1, A0 and DQ15A-1.
Nine bus write cycles are necessary to issue the command:
1.
2.
3.
4.
5.
6.
7.
8.
9.
To perform the Quadruple Byte Program command, it is necessary to apply V
V
Double Word Program command
The Double Word Program command is used to write a page of two adjacent Words in
parallel. The two Words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double Word Program command.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations will continue to output
the Status Register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical Program times are given in
Endurance
PP
/WP pin.
The first bus cycle sets up the command.
The second bus cycle latches the Address and the Data of the first Byte to be written.
The third bus cycle latches the Address and the Data of the second Byte to be written.
The fourth bus cycle latches the Address and the Data of the third Byte to be written.
The fifth bus cycle latches the Address and the Data of the fourth Byte to be written.
The sixth bus cycle latches the Address and the Data of the fifth Byte to be written.
The seventh bus cycle latches the Address and the Data of the sixth Byte to be written.
The eighth bus cycle latches the Address and the Data of the seventh Byte to be
written.
The ninth bus cycle latches the Address and the Data of the eighth Byte to be written
and starts the Program/Erase Controller.
The first bus cycle sets up the Quadruple Word Program Command.
The second bus cycle latches the Address and the Data of the first Word to be written.
The third bus cycle latches the Address and the Data of the second Word to be written
and starts the Program/Erase Controller.
PPH
on the V
cycles.
PP
/WP pin. For other devices, applying V
Table 8: Program, Erase times and Program, Erase
(2)
PPH
on the V
PP
/WP pin is mandatory.
PPH
to the