LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 57

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
MLVDS
The LA-LatticeXP2 devices support the differential MLVDS standard. This standard is emulated using complemen-
tary LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The MLVDS input standard is
supported by the LVDS differential input buffer. The scheme shown in Figure 3-5 is one possible solution for
MLVDS standard implementation. Resistor values in Figure 3-5 are industry standard values for 1% resistors.
Figure 3-5. MLVDS (Reduced Swing Differential Standard)
Table 3-5. MLVDS DC Conditions
For further information on LVPECL, RSDS, MLVDS, BLVDS and other differential interfaces please see details of
additional technical information at the end of this data sheet.
16mA
16mA
V
Z
R
R
R
V
V
V
V
I
1. For input buffer, see LVDS table.
DC
Parameter
OUT
OH
OL
OD
CCIO
CM
S
TL
TR
2.5V
2.5V
2.5V
2.5V
+
+
-
-
35ohms
35ohms
Output Driver Supply (+/-5%)
Driver Impedance
Driver Series Resistor (+/-1%)
Driver Parallel Resistor (+/-1%)
Receiver Termination (+/-1%)
Output High Voltage (After R
Output Low Voltage (After R
Output Differential Voltage (After R
Output Common Mode Voltage
DC Output Current
R
R
S
S
=
=
R
TL
2.5V
50 to 70 ohms +/-1%
1
1
6
m
35ohms
A
R
S
Description
Heavily loaded backplace, effective Zo~50 to 70 ohms differential
=
2.5V
1
6
m
35ohms
A
R
S
=
TL
TL
)
)
3-13
. . .
. . .
TL
)
2.5V
1
6
Zo=50¾
m
10.00
35.00
50.00
50.00
21.74
50 to 70 ohms +/-1%
A
2.50
1.52
0.98
0.54
1.25
35ohms
R
S
DC and Switching Characteristics
2.5V
=
LA-LatticeXP2 Family Data Sheet
Typical
1
6
m
A
35ohms
R
Zo=70¾
S
10.00
35.00
70.00
70.00
20.00
=
2.50
1.25
1.60
0.90
0.70
35ohms
35ohms
R
R
R
TR
S
S
=
=
Units
mA
¾
¾
¾
¾
V
V
V
V
V
2.5V
2.5V
+
-
16mA
16mA