LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 37

• Manufacturer Part Number: LAXP2-17E-5FTN256E
• Description: IC FPGA AUTO 17K LUTS 256-BGA
• Manufacturer: Lattice

Specifications of LAXP2-17E-5FTN256E

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
DQSXFER
LA-LatticeXP2 devices provide a DQSXFER signal to the output buffer to assist it in data transfer to DDR memories
that require DQS strobe be shifted 90
signal runs the span of the data bus.
sysIO Buffer
Each I/O is associated with a • exible buffer referred to as a sysIO buffer. These buffers are arranged around the
periphery of the device in groups referred to as banks. The sysIO buffers allow users to implement the wide variety
of standards that are found in today’s systems including LVCMOS, SSTL, HSTL, LVDS and LVPECL.
sysIO Buffer Banks
LA-LatticeXP2 devices have eight sysIO buffer banks for user I/Os arranged two per side. Each bank is capable of
supporting multiple I/O standards. Each sysIO bank has its own I/O supply voltage (V
has voltage references, V
shows the eight banks and their associated supplies.
In LA-LatticeXP2 devices, single-ended output buffers and ratioed input buffers (LVTTL, LVCMOS and PCI) are
powered using V
independent of V
Each bank can support up to two separate V
enced input buffers. Some dedicated I/O pins in a bank can be configured to be a reference voltage supply pin.
Each I/O is individually configurable based on the bank’s supply and reference voltages.
Figure 2-32. LA-LatticeXP2 Banks
CCIO
CCIO
. LVTTL, LVCMOS33, LVCMOS25 and LVCMOS12 can also be set as fixed threshold inputs
.
V
V REF1(7)
V REF2(7)
V CCIO6
V REF1(6)
V REF2(6)
CCIO7
REF1
GND
GND
and V
REF2
o
. This shifted DQS strobe is generated by the DQSDEL block. The DQSXFER
, that allow it to be completely independent from the others. Figure 2-32
REF
Bank 0
Bank 5
voltages, V
BOTTOM
2-34
TOP
REF1
Bank 1
Bank 4
and V
LA-LatticeXP2 Family Data Sheet
REF2
, that set the threshold for the refer-
V CCIO2
V REF1(2)
V REF2(2)
V CCIO3
V REF1(3)
V REF2(3)
GND
GND
CCIO
). In addition, each bank
Architecture