LAXP2-17E-5FTN256E Lattice, LAXP2-17E-5FTN256E Datasheet - Page 5
LAXP2-17E-5FTN256E
Manufacturer Part Number
LAXP2-17E-5FTN256E
Description
IC FPGA AUTO 17K LUTS 256-BGA
Manufacturer
Lattice
Datasheet
1.LAXP2-5E-5TN144E.pdf
(83 pages)
Specifications of LAXP2-17E-5FTN256E
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Lattice Semiconductor
Figure 2-1. Simplified Block Diagram, LA-LatticeXP2-17 Device (Top Level)
PFU Blocks
The core of the LA-LatticeXP2 device is made up of logic blocks in two forms, PFUs and PFFs. PFUs can be pro-
grammed to perform logic, arithmetic, distributed RAM and distributed ROM functions. PFF blocks can be pro-
grammed to perform logic, arithmetic and ROM functions. Except where necessary, the remainder of this data
sheet will use the term PFU to refer to both PFU and PFF blocks.
Each PFU block consists of four interconnected slices, numbered Slice 0 through Slice 3, as shown in Figure 2-2.
All the interconnections to and from PFU blocks are from routing. There are 50 inputs and 23 outputs associated
with each PFU block.
Programmable
Function Units
(PFUs)
sysMEM Block
RAM
DSP Blocks
SPI Port
On-chip
Oscillator
sysCLOCK PLLs
2-2
Flexible Routing
sysIO Buffers,
Pre-Engineered Source
Synchronous Support
LA-LatticeXP2 Family Data Sheet
Architecture
JTAG Port
Flash