LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 91
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 91 of 389
- Download datasheet (5Mb)
Lattice Semiconductor
Table 3-9. Channel Output Jitter - x20 Mode
Table 3-10. SERDES/PCS Latency Breakdown (Parallel Clock Cycle)
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Note: Values are measured with PRBS 2
x20 mode.
Transmit Data Latency
Receive Data Latency
1. PCS internal parallel clock. This clock rate is the same as rxfullclk.
2. FPGA Bridge latency varies by the upsample/downsample FIFO read/write. The numbers given are for the 8b10b interface. The
3. 1 = -245ps, 2 = 700ps
Description
depth of the downsample/upsample FIFO is 4. The earliest read can be done after the write clock cycle (one clock) in downsample
FIFO. The latest read will be done after the FIFO is full (4 + 1 = 5). For the 16b20b interface, the numbers are doubled: min. = 2, max.
= 10. This latency depends on the internal FIFO flag operation.
Item
R1
T4
T1
T2
T3
R2
R3
R4
R5
R6
3
3
FPGA Bridge Transmit
8b10b Encoder
SERDES Bridge Transmit
Serializer: 8-bit mode
Serializer: 10-bit mode
Deserializer: 8-bit mode
Deserializer: 10-bit mode
SERDES Bridge Receive
Word Alignment
8b10b Decoder
Clock Tolerance Compensation
FPGA Bridge Receive
3.125 Gbps
3.125 Gbps
3.125 Gbps
Frequency
1.25 Gbps
1.25 Gbps
1.25 Gbps
2.5 Gbps
2.5 Gbps
2.5 Gbps
Description
7
-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock at
2
2
Min.
—
—
—
—
—
—
—
—
—
Min.
3.1
—
—
—
—
—
—
—
—
1
7
1
3-39
Average
—
15
—
—
—
—
—
—
—
—
3
3
Typ.
0.08
0.27
0.35
0.09
0.23
0.29
0.05
0.16
0.20
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Max.
—
—
—
—
—
—
—
—
23
5
4
5
15 +
18 +
10 +
12 +
Fixed
Max.
—
0.19
0.11
0.12
0.51
0.59
0.34
0.45
0.22
0.28
2
2
2
1
1
1
2
2
Bypass
—
—
—
—
1
1
0
1
1
1
1
1
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
Units
word clk
word clk
word clk
word clk
word clk
word clk
word clk
word clk
UI + ps
UI + ps
UI + ps
UI + ps
Units
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