LFE2-20E-5FN256I Lattice, LFE2-20E-5FN256I Datasheet - Page 309
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFE2-20E-5FN256I
Manufacturer Part Number
LFE2-20E-5FN256I
Description
IC FPGA 21KLUTS 193I/O 256FPBGA
Manufacturer
Lattice
Series
ECP2r
Datasheets
1.LFE2-12SE-6FN256C.pdf
(389 pages)
2.LFE3-35EA-8FN672I.pdf
(21 pages)
3.LFE2-20E-5FN256I.pdf
(4 pages)
4.LFE2-20E-5FN256I.pdf
(769 pages)
Specifications of LFE2-20E-5FN256I
Number Of Logic Elements/cells
21000
Number Of Labs/clbs
2625
Total Ram Bits
282624
Number Of I /o
193
Number Of Gates
-
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
256-BGA
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
220-1170
LFE2-20E-5FN256I
Q6411457
LFE2-20E-5FN256I
Q6411457
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2-20E-5FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- LFE2-12SE-6FN256C PDF datasheet
- LFE3-35EA-8FN672I PDF datasheet #2
- LFE2-20E-5FN256I PDF datasheet #3
- LFE2-20E-5FN256I PDF datasheet #4
- Current page: 309 of 389
- Download datasheet (5Mb)
LFE2M100E/SE Logic Signal Connections: 900 fpBGA
Lattice Semiconductor
Ball Number
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
GNDIO
D2
D3
H7
G6
D1
G5
G4
G3
H5
H4
G2
G1
H3
H2
N8
M9
E3
E4
F5
E2
K7
K8
E1
F2
F1
K6
K5
J8
J5
J4
L9
L7
L8
L6
J3
-
Ball/Pad Function
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
GNDIO7
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL17A
PL17B
PL18A
PL18B
PL25A
PL25B
PL26A
PL26B
PL28A
PL28B
PL29A
PL29B
PL30A
PL30B
PL31A
PL31B
PL32A
PL32B
PL33A
PL33B
PL34A
PL9A
PL9B
-
LFE2M100E/SE
Bank
4-206
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
-
-
-
-
-
-
-
LUM0_SPLLC_FB_A/LDQ15
LUM0_SPLLT_FB_A/LDQ15
LUM0_SPLLC_IN_A/LDQ15
LUM0_SPLLT_IN_A/LDQ15
LatticeECP2/M Family Data Sheet
Dual Function
VREF2_7
VREF1_7
LDQS15
LDQS32
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ15
LDQ23
LDQ23
LDQ23
LDQ23
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
LDQ32
Pinout Information
Differential
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
C (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
T (LVDS)*
C
C
C
C
C
C
C
C
C
T
T
T
T
T
T
T
T
T
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