SI5374B-A-GL Silicon Laboratories Inc, SI5374B-A-GL Datasheet - Page 56

• Manufacturer Part Number: SI5374B-A-GL
• Description: Clock Synthesizer / Jitter Cleaner QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5374B-A-GL

• Package / Case: PBGA-80
• Input Level: LVCMOS
• Max Input Freq: 525 Hz
• Max Output Freq: 808 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Outputs: 8
• Output Level: LVCMOS
• Supply Current: 1100 mA
• Supply Voltage (max): 2.8 V
• Supply Voltage (min): - 0.5 V
• Lead Free Status / Rohs Status: Compliant

Si5374
Note: Internal register names are indicated by italics, e.g., IRQ_PIN . See Si5374 Register Map.
56
Pin #
G5
G6
D1
A6
F9
J4
Pin Name
CS_CA_A
CS_CA_B
CS_CA_C
CS_CA_D
SDA
SCL
Table 9. Si5374 Pin Descriptions (Continued)
I/O
I/O
I/O
I
LVCMOS DSPLLq Input Clock Select/Active Clock Indicator.
LVCMOS I
LVCMOS I
Signal
Level
Preliminary Rev. 0.4
Input: In manual clock selection mode, this pin functions as the
manual input clock selector if the CKSEL_PIN is set to 1.
0 = Select CKIN1
1 = Select CKIN2
If CKSEL_PIN = 0, the CKSEL_REG register bit controls this
function and this input tristates. If configured for input, must be
tied high or low.
Output: In automatic clock selection mode, this pin indicates
which of the two input clocks is currently the active clock. If
alarms exist on both clocks, CK_ACTV will indicate the last active
clock that was used before entering the digital hold state. The
CK_ACTV_PIN register bit must be set to 1 to reflect the active
clock status to the CK_ACTV output pin.
0 = CKIN1 active input clock
1 = CKIN2 active input clock
If CK_ACTV_PIN = 0, this pin will tristate. The CK_ACTV status
will always be reflected in the CK_ACTV_REG read only register
bit.
This pin functions as the serial clock input.
This pin has a weak pull-down.
I
2
2
2
C pin functions as the bi-directional serial data port.
C Serial Clock.
C Serial Data.
Description