SI5374B-A-GL Silicon Laboratories Inc, SI5374B-A-GL Datasheet - Page 18

• Manufacturer Part Number: SI5374B-A-GL
• Description: Clock Synthesizer / Jitter Cleaner QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5374B-A-GL

• Package / Case: PBGA-80
• Input Level: LVCMOS
• Max Input Freq: 525 Hz
• Max Output Freq: 808 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Outputs: 8
• Output Level: LVCMOS
• Supply Current: 1100 mA
• Supply Voltage (max): 2.8 V
• Supply Voltage (min): - 0.5 V
• Lead Free Status / Rohs Status: Compliant

Si5374
5. Register Descriptions
Reset value = 0001 0100
18
Register 0.
Name
Type
4:2
Bit
Bit
7
6
5
1
0
ALWAYS_ON
FREE_RUN
BYPASS_
Reserved
Reserved
Reserved
CKOUT_
D7
R
Name
REG
FREE_RUN CKOUT_ALWAYS_ON
R/W
D6
Free Run.
Internal to the device, route XA/XB to CKIN2. This allows the DSPLL to lock to its XA-XB
reference to support free-running clock generation.
0: Disable
1: Enable
CKOUT Always On.
This will bypass the SQ_ICAL function. Output will be available even if SQ_ICAL is on
and ICAL is not complete or successful. See Table 8 on page 52.
0: Squelch output until device is calibrated (ICAL).
1: Provide an output.
Notes:
Bypass Register.
This bit enables or disables PLL bypass mode. Use only when the device is in digital hold
or before the first ICAL. Bypass mode does not support CMOS clock outputs.
0: Normal operation
1: Bypass mode. Selected input clock is connected to CKOUT buffers, bypassing PLL.
1. The frequency may be significantly off until the device is calibrated.
2. Must be set to 1 to control output to output skew.
R/W
D5
Preliminary Rev. 0.4
D4
R
Function
D3
R
D2
R
BYPASS_REG
R/W
D1
D0
R