SI5374B-A-GL Silicon Laboratories Inc, SI5374B-A-GL Datasheet - Page 29
![Clock Synthesizer / Jitter Cleaner QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT](/photos/40/31/403184/si5374_sml.jpg)
SI5374B-A-GL
Manufacturer Part Number
SI5374B-A-GL
Description
Clock Synthesizer / Jitter Cleaner QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT
Manufacturer
Silicon Laboratories Inc
Datasheet
1.SI5374B-A-GL.pdf
(64 pages)
Specifications of SI5374B-A-GL
Package / Case
PBGA-80
Input Level
LVCMOS
Max Input Freq
525 Hz
Max Output Freq
808 MHz
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Number Of Outputs
8
Output Level
LVCMOS
Supply Current
1100 mA
Supply Voltage (max)
2.8 V
Supply Voltage (min)
- 0.5 V
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
SI5374B-A-GL
Manufacturer:
SILICON
Quantity:
1 001
Company:
Part Number:
SI5374B-A-GL
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Reset value = 1111 1111
Register 21.
Name
Type
7:6
5:2
Bit
Bit
1
0
CK1_ACTV_PIN CK1_ACTV_PIN.
CKSEL_PIN
Reserved
Write 0
Write 0
Name
D7
W
Write zero.
The CK1_ACTV_REG status bit can be reflected to the CS_CA output pin using the
CK1_ACTV_PIN enable function. CK1_ACTV_PIN is of consequence only when pin
controlled clock selection is being used.
0: CS_CA output pin tristated.
1: Clock Active status reflected to output pin.
CKSEL_PIN.
If manual clock selection is used, clock selection can be controlled via the
CKSEL_REG[1:0] register bits or the CS_CA input pin. This bit is only active when
AUTOSEL_REG = Manual.
0: CS_CA pin ignored. CKSEL_REG[1:0] register bits control clock selection.
1: CS_CA input pin controls clock selection.
Write 0
D6
W
D5
R
Preliminary Rev. 0.4
D4
R
D3
R
Function
D2
R
CK1_ACTV_PIN
R/W
D1
Si5374
CKSEL_ PIN
R/W
D0
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