SI5374B-A-GL Silicon Laboratories Inc, SI5374B-A-GL Datasheet - Page 16

• Manufacturer Part Number: SI5374B-A-GL
• Description: Clock Synthesizer / Jitter Cleaner QUAD DSPLL JITT ATT CLK LO LP BW 8IN/OUT
• Manufacturer: Silicon Laboratories Inc

Specifications of SI5374B-A-GL

• Package / Case: PBGA-80
• Input Level: LVCMOS
• Max Input Freq: 525 Hz
• Max Output Freq: 808 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Number Of Outputs: 8
• Output Level: LVCMOS
• Supply Current: 1100 mA
• Supply Voltage (max): 2.8 V
• Supply Voltage (min): - 0.5 V
• Lead Free Status / Rohs Status: Compliant

Reg.
10
19
20
21
22
23
24
25
31
32
11
Si5374
4. Register Map
The Si5374 has four identical register maps for each DSPLL. Each DSPLL has a unique I
independent control and device configuration. The I
corresponding DSPLL [A1] [A0] address is fixed as below.
Note: The Si5374 register map is similar, but not identical, to the Si5324 device.
All register bits that are not defined in this map should always be written with the specific reset values. Writing to
these bits with values other than the specified reset values may result in undefined device behavior. Registers not
listed, such as Register 64, should never be written to.
16
0
1
2
3
4
5
6
7
8
9
FOS_EN
AUTOSEL_REG[1:0]
Write 0
DSPLLA:
DSPLLB:
DSPLLC:
DSPLLD:
CKSEL_REG[1:0]
D7
HLOG_2[1:0]
ICMOS[1:0]
N1_HS[2:0]
FREE_RU
[A1] [A0]
Write 0
0
0
1
1
D6
BWSEL_REG[3:0]
N
FOS_THR[1:0]
0
1
0
1
ALWAYS_ON
HIST_AVG[4:0]
CKOUT_
DHOLD
D5
HLOG_1[1:0]
SFOUT2_REG[2:0}
Table 7. Si5374 Registers
SQ_ICAL
Preliminary Rev. 0.4
D4
VALTIME[1:0]
2
NC1_LS[15:8]
C address is 11010 [A1] [A0] for the entire device. Each
DSBL2_ REG
CK_ACTV_
Write 0
POL
D3
CK_PRIOR2[1:0]
DSBL1_ REG
LOS2_MSK
FOS2_MSK
HIST_DEL[4:0]
Write 0
D2
RATE_REG [3:0]
NC1_LS[19:16]
SFOUT1_REG[2:0]
FOSREFSEL[2:0]
BYPASS_REG
CK1_ACTV_PI
LOS1_MSK
FOS1_MSK
LOCKT[2:0]
LOL_POL
LOL_PIN
PD_CK2
D1
N
2
CK_PRIOR1[1:0]
C address enabling
CKSEL_PIN
LOSX_MSK
LOL_MSK
INT_POL
PD_CK1
IRQ_PIN
D0