MT9M001C12STM-EVAL Micron Technology Inc, MT9M001C12STM-EVAL Datasheet - Page 16

• Manufacturer Part Number: MT9M001C12STM-EVAL
• Manufacturer: Micron Technology Inc

Specifications of MT9M001C12STM-EVAL

• Lead Free Status / Rohs Status: Compliant

Table 7:
PDF: 09005aef81c2856f/Source: 09005aef80a3e031
MT9M001_DS_2.fm - Rev. F 5/06 EN
Register
Pixel Integration Control
These registers (along with the window sizing and blanking registers) control the integration time for the pixels.
The actual total integration time (
Reset delay = 4 x Reg0x0C pixel clock periods
If the value in Reg0x0C exceeds (row time - 548)/4 pixel clock cycles, the row time will be extended by (4 x Reg0x0C - (row
time - 548)) pixel clock cycles.
In this expression, the row time term, Reg0x09 x ((number of columns) + 244 + horizontal blanking register - 19),
corresponds to the number of rows integrated. The overhead time (180 pixel clocks) is the overhead time between the
READ cycle and the RESET cycle, and the final term is the effect of the reset delay.
Typically, the value of Reg0x09 is limited to the number of rows per frame (which includes vertical blanking rows) such
that the frame rate is not affected by the integration time. If Reg0x09 is increased beyond the total number of rows per
frame, the MT9M001 will add additional blanking rows as needed. A second constraint is that
avoid banding in the image from light flicker. Under 60Hz flicker, this means
Under 50Hz flicker,
Frame Restart
Reset
0x0C
0x0B
0x0D
0x09
t
Row time = ((Reg0x04 + 1) + 244 + Reg0x05 - 19) pixel clock periods
Overhead time = 180 pixel clock periods
INT = Reg0x09 x row time - overhead time - reset delay, where:
Register Description (continued)
13:0
10:0
Bit
0
0
t
INT must be a multiple of 1/100 of a second.
Number of rows of integration
Shutter delay
and control logic waits before asserting the reset for a given row.
Setting bit 0 to “1” of Reg0x0B will cause the sensor to abandon the readout of the current frame
and restart from the first row. This register automatically resets itself to 0x0000 after the frame
restart. The first frame after this event is considered to be a "bad frame" (see description for
Reg0x20, bit0).
This register is used to reset the sensor to its default, power-up state. To put the MT9M001 in reset
mode first write a “1” into bit 0 of this register, then write a “0” into bit 0 to resume operation.
t
INT) is:
—
default = 0x0000 (0). This is the number of master clocks times four that the timing
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
—
default = 0x0419 (1049).
16
Description
Micron Technology, Inc., reserves the right to change products or specifications without notice.
t
INT must be a multiple of 1/120 of a second.
t
©2004 Micron Technology, Inc. All rights reserved.
INT must be adjusted to
Registers