MT9M001C12STM-EVAL Micron Technology Inc, MT9M001C12STM-EVAL Datasheet - Page 12

• Manufacturer Part Number: MT9M001C12STM-EVAL
• Manufacturer: Micron Technology Inc

Specifications of MT9M001C12STM-EVAL

• Lead Free Status / Rohs Status: Compliant

Stop Bit
Slave Address
Data Bit Transfer
Acknowledge Bit
No-Acknowledge Bit
PDF: 09005aef81c2856f/Source: 09005aef80a3e031
MT9M001_DS_2.fm - Rev. F 5/06 EN
The stop bit is defined as a LOW-to-HIGH transition of the data line while the clock line
is HIGH.
The 8-bit address of a two-wire serial interface device consists of seven bits of address
and 1 bit of direction. A “0” (0xBA) in the LSB (least significant bit) of the address indi-
cates the write mode, and a “1” (0xBB) indicates read mode.
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the HIGH period of the two-wire
serial interface clock—it can only change when the serial clock is LOW. Data is trans-
ferred eight bits at a time, followed by an acknowledge bit.
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indi-
cates an acknowledge bit by pulling the data line LOW during the acknowledge clock
pulse.
The no-acknowledge bit is generated when the data line is not pulled down by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
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Micron Technology, Inc., reserves the right to change products or specifications without notice.
Serial Bus Description
©2004 Micron Technology, Inc. All rights reserved.