TS68C429AMFA E2V, TS68C429AMFA Datasheet - Page 4

• Manufacturer Part Number: TS68C429AMFA
• Manufacturer: E2V

Specifications of TS68C429AMFA

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / Rohs Status: Compliant

2. Package
Table 2-1.
4
Pin Name
A0-8
D0-15
CS
LDS
UDS
R/W
DTACK
IRQTX
IACKTX
IEITX
IEOTX
IRQRX
IACKRX
IEIRX
IEORX
TX1H
TX1L
TX2H
TX2L
TX3H
TX3L
RX1H
0848E–HIREL–02/08
Signal Description
See
Type
“Package Mechanical Data” on page 41
I/O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
Function
Address bus. The address bus is used to select one of the internal registers during a processor
read or write cycle.
This bi-directional bus is used to receive data from or transmit data to an internal register during a
processor read or write cycle. During an interrupt acknowledge cycle, the vector number is given
on the lower data bus (D0 - D7).
Chip select (active low). This input is used to select the chip for internal register access.
Lower data strobe. This input (active low) validates lower data during R/W access (D0-D7).
Upper data strobe. This input (active low) validates upper data during R/W access (D8-D15).
Read/write. This input defines a data transfer as a read (high) or a write (low) cycle.
Data transfer acknowledge. If the bus cycle is a processor read, the chip asserts DTACK to
indicate that the information on the data bus is valid. If the bus cycle is a processor write, DTACK
acknowledges the acceptance of the data by the MRT. DTACK will be asserted during chip select
access (CS asserted) or interrupt acknowledge cycle (IACKTX or IACKRK asserted).
Interrupt transmit request. This open drain output signals to the processor that an interrupt is
pending from the transmission part of the MRT. There are 6 causes that can generate an interrupt
request (2 per channel: FIFO empty and end of transmission).
Interrupt transmit acknowledge. If IRQTX is active, the MRT will begin an interrupt acknowledge
cycle. The MRT will generate a vector number to the processor which is the highest priority
channel requesting interrupt service.
Interrupt transmit enable in. This input, together with IEOTX signal, provides a daisy chained
interrupt structure for a vectored scheme. IEITX (active low) indicates that no higher priority
device is requesting interrupt service.
Interrupt transmit enable out. This output, together with IEITX signal, provides a daisy chained
interrupt structure for a vectored interrupt scheme. IEOTX (active low) indicates to lower priority
devices that neither the TS68C429A nor any highest priority peripheral is requesting an interrupt.
Interrupt transmit request. This open drain output signals to the processor that an interrupt is
pending from the receiving part of the chip. There are 9 causes that can generate an interrupt
request (1 per channel: valid message received, and 1 for bad parity on a received message).
Interrupt receive acknowledge. Same function as IACKTX but for receiver part.
Interrupt receive enable in. Same function as IEITX but for receiver part.
Interrupt receive enable out. Same function as IEOTX but for receiver part.
Transmission “1” line of the channel 1.
Transmission “0” line of the channel 1.
Transmission “1” line of the channel 2.
Transmission “0” line of the channel 2.
Transmission “1” line of the channel 3.
Transmission “0” line of the channel 3.
Receiving “1” line of the channel 1.
and
“Terminal Connections” on page
e2v semiconductors SAS 2008
42.
TS68C429A