TS68C429AMFA E2V, TS68C429AMFA Datasheet - Page 2

• Manufacturer Part Number: TS68C429AMFA
• Manufacturer: E2V

Specifications of TS68C429AMFA

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Pin Count: 132
• Lead Free Status / Rohs Status: Compliant

Application Note
1. Hardware Overview
2
0848E–HIREL–02/08
The TS68C429A is a high performance ARINC 429 controller designed to interface primary to the
TS68K family microprocessor in a straight forward fashion (see
be connected to any TS68K processor family with an asynchronous bus with some additional logic in
some cases.
As shown in
interface unit (MIU), the logical control unit (LCU), the interrupt control unit (ICU), the receiver channel
unit (RCU) and the transmitter channel unit (TCU).
• A detailed application note is available “AN 68C429A” on request.
• The MIU handles the interface protocol of the host processor. Through this unit, the host sees the
• The LCU controls the internal data flow and initializes the TS68C429A.
• The ICU manages one interrupt line for the RCU and one for the TCU. Each of these two parts has a
• The RCU is composed of 8 ARINC receiver channels made of:
• The TCU is composed of three ARINC transmitter channels made of:
• Test facility: Rx inputs can be internally connected to TX3 output.
• Self-test facility: The receiver control label matrix and transmitter FIFO can be tested. This self-test
TS68C429A as a set of registers.
daisy chain capability. All channels have a dedicated vectored interrupt answer. Receiver channels
priority is programmable.
can be used to verify the integrity of the TS68C429A memories.
– a serial to parallel converter to translate the two serial signals (the “1” and “0” in RZ code)
– a memory to store the valid labels,
– a control logic to check the validity of the received message,
– a buffer to keep the last valid received message.
– a parallel to serial converter to translate the messages into two serial signals (the “1” and “0”
– a FIFO memory to store eight 32-bit ARINC messages,
– a control logic to synchronize the message transmitter (parity, gap, speed, etc.).
into two 16-bit words,
in RZ code),
Figure 1-1 on page
Ceramic Pin Grid Array
R suffix
PGA 84
3, the TS68C429A is divided into five main blocks, the microprocessor
Ceramic Quad Flat Pack
“Application Notes” on page
CQFP 132
F suffix
e2v semiconductors SAS 2008
TS68C429A
35). It can
e2v