KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 61
KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 61 of 190
- Download datasheet (6Mb)
2.6.1
The classic software debug approach (start/stop, single-stepping) is supported by
several features labelled “OCDS Level 1”:
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2.6.2
For detailed tracing of the system’s behavior a pin-compatible Emulation Device will be
available.
2.6.3
Two main use cases are catered for by resources in addition the OCDS Level 1
infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling:
•
•
1) The OCDS L2 interface of AudoNG is not available.
Data Sheet
Run/stop and single-step execution independently for TriCore and PCP.
Means to request all kinds of reset without usage of sideband pins.
Halt-after-Reset for repeatable debug sessions.
Different Boot modes to use application software not yet programmed to the Flash.
A total of four hardware breakpoints for the TriCore based on instruction address,
data address or combination of both.
Unlimited number of software breakpoints (DEBUG instruction) for TriCore and PCP.
Debug event generated by access to a specific address via the system bus.
Tool access to all SFRs and internal memories independent of the Cores.
Two central Break Switches to collect debug events from all modules (TriCore, PCP,
DMA, BCU, break input pins) and distribute them selectively to breakable modules
(TriCore, PCP, break output pins).
Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals)
instead if breaking them as reaction to a debug event.
Dedicated interrupt resources to handle debug events inside TriCore (breakpoint
trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing
Monitor programs.
Access to all OCDS Level 1 resources also for TriCore and PCP themselves for
debug tools integrated into the application code.
Triggered Transfer of data in response to a debug event; if target is programmed to
be a device interface simple variable tracing can be done.
In depth performance analysis and profiling support given by the Emulation Device
through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit,
wait state, interrupt accepted).
8 KB SRAM for Overlay.
Can be split into up to 16 blocks which can overlay independent regions of on-chip
Data Flash.
1)
On-Chip Debug Support
Real Time Trace
Calibration Support
57
Introduction
V1.1, 2009-04
TC1797
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