KIT_TC1797_SK Infineon Technologies, KIT_TC1797_SK Datasheet - Page 181
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KIT_TC1797_SK
Manufacturer Part Number
KIT_TC1797_SK
Description
KIT STARTER AUDO FUTURE TC1797
Manufacturer
Infineon Technologies
Series
Audo Futurer
Type
MCUr
Datasheets
1.SAK-TC1797-512F180E_AC.pdf
(190 pages)
2.KIT_TC1791_SK.pdf
(46 pages)
3.KIT_TC1797_SK.pdf
(101 pages)
4.KIT_TC1797_SK.pdf
(12 pages)
Specifications of KIT_TC1797_SK
Contents
Board, Adapters, Cables, CD, Power Supply
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
TC1797
Other names
KITTC1797SKIN
- SAK-TC1797-512F180E_AC PDF datasheet
- KIT_TC1791_SK PDF datasheet #2
- KIT_TC1797_SK PDF datasheet #3
- KIT_TC1797_SK PDF datasheet #4
- Current page: 181 of 190
- Download datasheet (6Mb)
5.3.11.2 Micro Second Channel (MSC) Interface Timing
Table 30
Parameter
FCLP clock period
SOP/ENx outputs delay
from FCLP rising edge
SDI bit time
SDI rise time
SDI fall time
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 ×
3)
Figure 41
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
Data Sheet
T
MSCmin
device.
FCLP
SOP
EN
SDI
=
T
SYS
MSC Interface Timing (Operating Conditions apply), C
MSC Interface Timing
= 1 /
f
1)2)
SYS
. When
t
45
f
SYS
Symbol
t
t
t
t
t
40
45
46
48
49
= 90 MHz,
t
46
CC 2 ×
CC -10
CC 8 ×
SR
SR
t
40
t
T
40
Min.
MSC
= 22,2ns
177
.
T
T
t
48
MSC
MSC
3)
t
Values
45
t
Typ.
–
46
Max.
–
10
–
100
100
t
Electrical Parameters
49
MSC_Tmg_1.vsd
Unit
ns
ns
ns
ns
ns
L
0.9
0.1
= 50 pF
0.9
0.1
V
V
V
V
V1.1, 2009-04
DDP
DDP
DDP
DDP
Note /
Test Con
dition
–
–
–
–
–
TC1797
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