AN983BX-BG-T-V1 Infineon Technologies, AN983BX-BG-T-V1 Datasheet - Page 87

• Manufacturer Part Number: AN983BX-BG-T-V1
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BX-BG-T-V1

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BXBGTV1; AN983BXBGTV1XP; SP000075554

Field
SPEED
ANE
PD
IS
RAN
DM
CT
Res
SC: Self Clearing
Reset: Reset this port only. This will cause the following:
1. Restart the autonegotiation process.
2. Reset the registers to their default values. Note that this does not affect registers 20, 22, 30 or 31. These
Note: No reset is performed to analogue sections of the port. There is also no physical reset to any internal clock
Loopback: Loop back of transmit data to receive via a path as close to the wire as possible. When set inhibits
actual transmission on the wire.
Speed selection: Forces speed of Phy only when autonegotiation is disabled. The default state of this bit will be
determined by a power-up configuration pin in this case. Otherwise it defaults to 1.
Auto-neg enable Defaults to pin programmed value. When cleared allows forcing of speed and duplex settings.
When set (after being cleared) causes re-start of autoneg process. Pin programming at power-up allows it to come
up disabled and for software to write the desired capability before allowing the first negotiation to commence.
Restart Negotiation: only has effect when autonegotiating. Restarts state machine.
Power down: Has no effect in this device. Test mode power down modes may be implemented in other specific
modules.
Isolate: Puts RMII receive signals into high impedance state and ignores transmit signals.
Duplex mode: When bit12 is cleared (i.e. autoneg disabled), this bit forces full duplex (bit = 1) or half duplex
(bit = 0).
Data Sheet
registers are not reset by this bit to allow test configurations to be written and then not to be affected by
resetting the port.
synthesizers or the local clock recovery oscillator which will continue to run throughout the reset period.
However since the port is restarted and autoneg re-run the process of locking the frequency of the local
oscillator (slave) to the reference oscillator (master) will be repeated as it is at the start of any link initialization
process.
Bits
13
12
11
10
9
8
7
6:0
Type
rw
rw
rw
rw
rwsc
rw
ro
ro
Registers and Descriptors DescriptionPHY Registers(Accessed by CSR9
Description
Speed Selection
0
1
Autonegotiation Enable
0
1
Power Down
0
1
Isolate
0
1
Restart Autonegotiation
1
Duplex Mode
0
1
Collision Test
Not implemented
Reserved
B
B
B
B
B
B
B
B
B
B
B
, 10 Mbit/s
, 100 Mbit/s
, disable autoneg
, enable autoneg
, normal operation
, Power Down
, normal operation
, isolate PHY from MII
, Restart Autoneg
, half duplex
, full duplex
87
Rev. 1.81, 2005-12-15
AN983B/BX