AN983BX-BG-T-V1 Infineon Technologies, AN983BX-BG-T-V1 Datasheet - Page 70

• Manufacturer Part Number: AN983BX-BG-T-V1
• Description: IC PCI TO ETHERNET LAN 128-PQFP
• Manufacturer: Infineon Technologies

Specifications of AN983BX-BG-T-V1

• Applications: Ethernet Controller
• Interface: USB
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 128-BFQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: AN983BXBGTV1; AN983BXBGTV1XP; SP000075554

Field
FBE
Res
GPTT
Res
RWT
RPS
RDU
RCI
TUF
Res
TJT
Data Sheet
Bits
13
12
11
10
9
8
7
6
5
4
3
Type
ro/lh
ro
ro/lh
ro
ro/lh
ro/lh
ro/lh
ro/lh
ro/lh
ro
ro/lh
Description
Fatal Bus Error
Note: LH = High Latching and cleared by writing 1
1
Reserved
General Purpose Timer Time-out
Base on CSR11 timer register.
Note: LH = High Latching and cleared by writing 1
Reserved
Receive Watchdog Time-out
Based on CSR15 watchdog timer register.
Note: LH = High Latching and cleared by writing 1
Receive Process Stopped
Receive state = stop
Note: LH = High Latching and cleared by writing 1
Receive Descriptor Unavailable
Note: LH = High Latching and cleared by writing 1
1
Receive Completed Interrupt
Note: LH = High Latching and cleared by writing 1
1
Transmit Under-Flow
Note: LH = High Latching and cleared by writing 1
1
Reserved
Transmit Jabber Timer Time-out
Note: LH = High Latching and cleared by writing 1
1
Registers and Descriptors DescriptionPCI Control/Status Registers
B
B
B
B
B
(see bits 25~23 of CSR5) AN983B/BX will disable all bus access.
The way to recover parity error is by setting software reset.
Receive process is suspended in this situation. To restart the
receive process the ownership bit of the next receive descriptor
should be set to AN983B/BX and a receive poll demand command
should be issued (or a new recognized frame is received, if the
receive poll demand is not issued).
happened during transmitting. The transmit process will enter the
suspended state and report the under-flow error on bit1 of TDES0
will enter the stop state and the transmit jabber time-out flag of bit
14 of TDES0 will be asserted
, while the next receive descriptor can’t be applied by AN983B/BX.
, while any of parity error master abort, or target abort is occurred
, while a frame reception is completed
, while the transmitting FIFO had an under-flow condition. It
, while the transmit jabber timer expired. The transmit processor
70
Rev. 1.81, 2005-12-15
AN983B/BX