ISD-300A1 Cypress Semiconductor Corp, ISD-300A1 Datasheet - Page 19

• Manufacturer Part Number: ISD-300A1
• Description: IC USB 2.0 BRIDGE BULK 100LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of ISD-300A1

• Applications: USB 2.0 to ATA/ATAPI Bridge
• Interface: ATA, ATAPI
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 100-LQFP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1459

October 19, 2001
Address
0xD
0xE
0xF
Table 4 – ISD-300A1 Configuration Bytes
USB Interface
The ISD-300A1 is electrically and logically compliant with the Universal Serial Bus Specification Revision
2.0.
Descriptors
Supported Descriptors
•
•
Device
USB Device Qualifier
The ISD-300A1 requires only one Device Qualifier descriptor. The information returned is
identical for full and high speed modes of operation.
PIO Mode Selection
Skip Pin Reset
General Purpose IO
General Purpose IO 3-
state control
General Purpose IO
General Purpose IO 3-
state control
Field Name
Bits (7:5)
PIO Mode Selection. The PIO mode reported back to the device if the
Override PIO Timing configuration bit is set. This field represents the PIO
mode of operation configured by the ATA Data Setup, ATA Data Assertion,
ATA Data Recover, and Override PIO Timing fields.
mode 0
mode 1
mode 2
mode 3
mode 4
Bit (4)
Skip ATA_NRESET assertion. Note: SRST Enable must be set in
conjunction with Skip Pin Reset. Setting this bit causes the Initialize
algorithm to bypass ATA_NRESET assertion unless a DISK_READY 0=>1
event occurred. All other reset events utilize SRST as the drive reset
mechanism.
0
1
Bits (3:2)
GPIO[9:8] input / output control
Writing this register controls the output state of the GPIO pin (if the 3-state
control is enabled)
Reading this register returns the logic value from the GPIO pin
Bits (1:0)
GPIO[9:8] 3-state control
0
1
Bits(7:0)
GPIO[7:0] input / output control
Writing this register controls the output state of the GPIO pin (if the 3-state
control is enabled)
Reading this register returns the logic value from the GPIO pin
Bits(7:0)
GPIO[7:0] 3-state control
0
1
Output enabled (GPIO pin is an output)
3-state(hi-Z) (GPIO pin is an input)
Output enabled (GPIO pin is an output)
3-state (hi-Z) (GPIO pin is an input)
Allow ATA_NRESET assertion for all resets
Disable ATA_NRESET assertion except for drive power-on reset
cycles
000
001
010
011
100
14
Description
ISD-300A1
ROM Defaults
On-board
0xFF
0x03
0x00