UJA1069TW24/5V0:51 NXP Semiconductors, UJA1069TW24/5V0:51 Datasheet - Page 15

• Manufacturer Part Number: UJA1069TW24/5V0:51
• Description: IC LIN FAIL-SAFE 24-HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1069TW24/5V0:51

• Applications: Automotive
• Interface: LIN (Local Interconnect Network)
• Voltage - Supply: 5V
• Package / Case: 24-TSSOP Exposed Pad, 24-eTSSOP, 24-HTSSOP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935280013518; UJA1069TW24/5V0-T; UJA1069TW24/5V0-T

NXP Semiconductors
UJA1069_3
Product data sheet
6.5.1 RSTN pin
6.5 System reset
The reset function of the UJA1069 offers two signals to deal with reset events:
The system reset pin (RSTN) is a bidirectional input / output. Pin RSTN is active LOW with
selectable pulse length upon the following events; see
All of these reset events have a dedicated reset source in the System Status register to
allow distinction between the different events.
The SBC will lengthen any reset event to 1 ms or 20 ms to ensure that external hardware
is properly reset. After the first battery connection, a short power-on reset of 1 ms is
provided after voltage V1 is present. Once started, the microcontroller can set the Reset
Length Control (RLC) bit within the System Configuration Register; this allows the reset
pulse to be adjusted for future reset events. With this bit set, all reset events are
lengthened to 20 ms. Due to fail-safe behavior, this bit will be set automatically (to 20 ms)
in Restart mode or Fail-safe mode. With this mechanism it is guaranteed that an
erroneously shortened reset pulse will restart any microcontroller, at least within the
second trial by using the long reset pulse.
The behavior of pin RSTN is illustrated in
setting of the RLC bit (defines the reset length). Once an external reset event is detected
the system controller enters the Start-up mode. The watchdog now starts to monitor pin
RSTN as illustrated in
mode is entered as shown in
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RSTN; the global ECU system reset
EN; a fail-safe global enable signal
Power-on (first battery connection) or V
Low V1 supply
V1 current above threshold during Standby mode while watchdog OFF behavior is
selected
V3 is down due to short-circuit condition during Sleep mode
RSTN externally forced LOW, falling edge event
Successful preparation for Flash mode completed
Successful exit from Flash mode
Wake-up from Standby mode via pins LIN or WAKE if programmed accordingly, or any
wake-up event from Sleep mode
Wake-up event from Fail-safe mode
Watchdog trigger failures (too early, overflow, wrong code)
Illegal mode code via SPI applied
Interrupt not served within t
Rev. 03 — 10 September 2007
Figure
Figure
8. If the RSTN pin is not released in time then Fail-safe
RSTN(INT)
4.
Figure
BAT42
7. The duration of t
below power-on reset threshold voltage
Figure
LIN fail-safe system basis chip
4:
RSTNL
UJA1069
© NXP B.V. 2007. All rights reserved.
depends on the
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