UJA1069TW24 NXP [NXP Semiconductors], UJA1069TW24 Datasheet
UJA1069TW24
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UJA1069TW24 Summary of contents
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UJA1069 LIN fail-safe system basis chip Rev. 03 — 10 September 2007 1. General description The UJA1069 fail-safe System Basis Chip (SBC) replaces basic discrete components which are common in every Electronic Control Unit (ECU) with a Local Interconnect Network ...
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NXP Semiconductors 2. Features 2.1 General I Contains a full set of LIN ECU functions: N LIN transceiver N Voltage regulator for the microcontroller (3 Enhanced window watchdog with on-chip oscillator N Serial ...
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... HTSSOP24 [1] UJA1069TW/5V0 is for the 5 V version; UJA1069TW/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version. [2] UJA1069TW24/5V0 is for the 5 V version; UJA1069TW24/3V3 is for the 3.3 V version; UJA1069TW/3V0 is for the 3 V version. UJA1069_3 Product data sheet Description plastic thermal enhanced thin shrink small outline package; 32 leads; ...
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... SDO 12 (11) SCS 26 (18) RTLIN 25 (17) LIN 3 (2) TXDL 5 (4) RXDL 23 (15) GND The pin numbers in parenthesis are for the UJA1069TW24 version. Fig 1. Block diagram UJA1069_3 Product data sheet BAT MONITOR INH SBC FAIL-SAFE SYSTEM SPI LIN BAT42 Rev. 03 — 10 September 2007 ...
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... UJA1069TW SDI 9 SDO 10 SCK 11 12 SCS n. n.c. TEST 16 001aad676 1 n.c. TXDL RXDL RSTN 5 INTN 6 UJA1069TW24 SDI SDO 9 SCK 10 11 SCS TEST 12 001aad677 Rev. 03 — 10 September 2007 UJA1069 LIN fail-safe system basis chip 32 BAT42 31 SENSE SYSINH 28 n.c. 27 BAT14 26 RTLIN ...
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NXP Semiconductors 5.2 Pin description Table 2. Symbol n.c. n.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCS n.c. n.c. n.c. TEST INH/LIMP WAKE n.c. n.c. n.c. n.c. GND n.c. LIN RTLIN BAT14 n.c. SYSINH UJA1069_3 Product data ...
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NXP Semiconductors Table 2. Symbol V3 SENSE BAT42 The exposed die pad at the bottom of the package allows better dissipation of heat from the SBC via the printed-circuit board. The exposed die pad is not connected to any active ...
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NXP Semiconductors mode change via SPI watchdog trigger Normal mode V1: ON SYSINH: HIGH flash entry enabled (111/001/111 mode sequence) LIN: all modes available OR mode change to Sleep with pending wake-up watchdog: window INH/LIMP: HIGH/LOW/float EN: HIGH/LOW init Normal ...
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NXP Semiconductors 6.2.1 Start-up mode Start-up mode is the ‘home page’ of the SBC. This mode is entered when battery and ground are connected for the first time. Start-up mode is also entered after any event that results in a ...
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NXP Semiconductors Interrupts from SBC to the host microcontroller are also monitored. A system reset is performed if the host microcontroller does not respond within t mode does not activate the LIN transceiver automatically. The LIN Mode Control (LMC) bit ...
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NXP Semiconductors When an interrupt event occurs the application software has to read the Interrupt register within t RSTN(INT) entered. If the application has read out the Interrupt register within the specified time, it can decide whether to switch into ...
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NXP Semiconductors operating mode codes 111, 001 and 111 respectively result of this sequence, the SBC will enter Start-up mode and perform a system reset with the related reset source information (bits RSS[3:0] = 0110). From Start-up mode ...
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NXP Semiconductors Any microcontroller driven mode change is synchronized with a watchdog access by reading the mode information and the watchdog period information from the same register. This enables an easy software flow control with defined watchdog behavior when switching ...
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NXP Semiconductors 6.4.3 Watchdog time-out behavior Whenever the SBC operates in Standby mode, in Sleep mode or in Flash mode, the active watchdog operates in Time-out mode. The watchdog has to be triggered within the actual programmed period time; see ...
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NXP Semiconductors 6.5 System reset The reset function of the UJA1069 offers two signals to deal with reset events: • RSTN; the global ECU system reset • EN; a fail-safe global enable signal 6.5.1 RSTN pin The system reset pin ...
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NXP Semiconductors V1 V RSTN Fig 7. Reset pin behavior Fig 8. Reset timing diagram Pin RSTN is monitored for a continuously clamped LOW situation. Once the SBC pulls pin RSTN HIGH but pin RSTN level remains LOW for longer ...
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NXP Semiconductors The SBC also detects if pin RSTN is clamped HIGH. If the HIGH-level remains on the pin for longer than t the SBC falls back immediately to Fail-safe mode since the microcontroller cannot be reset any more. By ...
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NXP Semiconductors 6.6.4 Switched battery output high-side switched BAT42-related output which is used to drive external loads such as wake-up switches or relays. The features of V3 are as follows: • Three application controlled modes of ...
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NXP Semiconductors Fig 9. States LIN transceiver 6.7.1.1 Active mode In Active mode the LIN transceiver can transmit data to and receive data from the LIN bus. To enter Active mode the LMC bit must be set in the Physical ...
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NXP Semiconductors Fig 10. LIN wake-up timing diagram 6.7.3 Termination control The RTLIN pin is in one of 3 different states: RTLIN = on, RTLIN = off or RTLIN = 75 A; see Figure RTLIN = ON supplied directly out ...
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NXP Semiconductors 6.7.5 LIN driver capability Setting the LDC bit in the Physical Layer Control register will increase the driver capability of the LIN output stage. This feature is used in auto-addressing systems, where the standard LIN 2.0 drive capability ...
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NXP Semiconductors INH/LIMP: HIGH ILEN = 1 ILC = 1 state change via SPI Fig 12. States of the INH/LIMP pin When pin INH/LIMP is used as inhibit output, a pull-down resistor to GND ensures a default LOW level. The ...
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NXP Semiconductors t on(CS su(CS) sample active signal already HIGH V WAKE due to biasing (history) flip flop V INTN Fig 13. Pin WAKE, cyclic sampling via V3 6.10 Interrupt output Pin INTN is an open-drain interrupt ...
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NXP Semiconductors 6.12 SPI interface The Serial Peripheral Interface (SPI) provides the communication link with the microcontroller, supporting multi-slave and multi-master operation. The SPI is configured for full duplex data transfer, so status information is returned when new control data ...
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NXP Semiconductors 6.12.1 SPI register mapping Any control bit which can be set by software is readable by the application. This allows software debugging as well as control algorithms to be implemented. Watchdog serving and mode setting is performed within ...
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NXP Semiconductors Table 4. Mode register bit description (bits and Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only NWP[5:0] see ...
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NXP Semiconductors Table 5. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 00 (as set in the Special Mode register) Nominal Watchdog Period WDPRE = 01 (as set ...
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NXP Semiconductors Table 5. Mode register bit description (bits Bit Symbol Description NWP[5:0] Nominal Watchdog Period WDPRE = 11 (as set in the Special Mode register) [1] The nominal watchdog periods are directly related ...
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NXP Semiconductors Table 6. System Status register bit description Bit Symbol Description RSS[3:0] Reset Source 7 - reserved 6 LWS LIN Wake-up Status 5 EWS Edge Wake-up Status 4 WLS WAKE Level Status 3 TWS Temperature Warning ...
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NXP Semiconductors Table 7. System Diagnosis register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only reserved 6 and 5 LINFD[1:0] LIN failure diagnosis ...
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NXP Semiconductors Table 8. Interrupt Enable and Interrupt Enable Feedback register bit description Bit Symbol Description 7 BATFIE BAT Failure Interrupt Enable 6 VFIE Voltage Failure Interrupt Enable 5 - reserved 4 LINFIE LIN Failure Interrupt Enable 3 WIE WAKE ...
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NXP Semiconductors Table 9. Interrupt register bit description Bit Symbol Description 15 and 14 A1, A0 register address 13 RRS Read Register Select 12 RO Read Only 11 WTI Watchdog Time-out Interrupt 10 OTI OverTemperature Interrupt 9 - reserved 8 ...
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NXP Semiconductors Table 10. System Configuration and System Configuration Feedback register bit description Bit Symbol Description 12 RO Read Only 11 and 10 - reserved 9 - reserved 8 RLC Reset Length Control 7 and 6 V3C[1:0] V3 Control 5 ...
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NXP Semiconductors Table 11. Physical Layer Control and Physical Layer Control Feedback register bit description Bit Symbol Description 12 RO Read Only reserved 4 LMC LIN Mode Control 3 LSC LIN Slope Control 2 LDC LIN ...
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NXP Semiconductors Table 12. Special Mode register and Special Mode Feedback register bit description Bit Symbol Description 4 and 3 V1RTHC[1:0] V1 Reset Threshold Control reserved [1] See Section 6.13.1. [2] Not supported for the UJA1069TW/3V0 ...
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NXP Semiconductors Table 14. General Purpose register 1 and General Purpose Feedback register 1 bit description Bit Symbol Description 12 RO Read Only GP1[11:0] General Purpose bits 6.12.12 Register configurations at reset At Power-on, Start-up and Restart ...
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NXP Semiconductors Table 19. System Configuration register and System Configuration Feedback register: status at reset Symbol Name RLC Reset Length Control V3C V3 Control V1CMC V1 Current Monitor Control WEN Wake Enable WSC Wake Sample Control ILEN INH/LIMP Enable ILC ...
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NXP Semiconductors 6.13 Test modes 6.13.1 Software development mode The Software development mode is intended to support software developers in writing and pretesting application software without having to work around watchdog triggering and without unwanted jumps to Fail-safe mode. In ...
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NXP Semiconductors 6.13.2 Forced normal mode For system evaluation purposes the UJA1069 offers the Forced normal mode. This mode is strictly for evaluation purposes only. In this mode the characteristics as defined in Section 9 In Forced normal mode the ...
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NXP Semiconductors 7. Limiting values Table 24. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). All voltages are referenced to GND. Symbol Parameter V BAT42 supply voltage BAT42 V BAT14 supply voltage BAT14 V DC voltage ...
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NXP Semiconductors 8. Thermal characteristics Fig 15. Thermal model of the HTSSOP32 package Fig 16. Thermal model of the HTSSOP24 package UJA1069_3 Product data sheet V1 dissipation V3 dissipation 6 K/W 23 K/W 6 K/W T (heat sink) case R ...
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NXP Semiconductors 9. Static characteristics Table 25. Static characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol ...
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NXP Semiconductors Table 25. Static characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Battery supply ...
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NXP Semiconductors Table 25. Static characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I output ...
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NXP Semiconductors Table 25. Static characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I input ...
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NXP Semiconductors Table 25. Static characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter V LIN ...
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NXP Semiconductors Table 25. Static characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter I RTLIN ...
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NXP Semiconductors Fig 17. V1 output voltage (dropout function of battery voltage UJA1069_3 Product data sheet 100 120 mA 250 ...
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NXP Semiconductors I BAT14 (mA) (1) Types 5V0, 3V3 and 3V0. (2) Type 5V0 only BAT14 (mA) (1) Types 5V0, 3V3 and 3V0. (2) Types 3V3 and 3V0 Fig 18. V1 quiescent current ...
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NXP Semiconductors V (V) Fig 19. V1 output voltage as a function of output current PSRR (dB) (1) Type 5V0 only. Fig 20. V1 power supply ripple rejection as a function of frequency UJA1069_3 Product data sheet 6 type 5V0 ...
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NXP Semiconductors V BAT14 (V) a. Line transient response I (mA) b. Load transient response Fig 21. V1 transient response as a function of time UJA1069_3 Product data sheet 16 V BAT14 100 200 I = ...
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NXP Semiconductors ESR ( ) Fig 22. V1 output stability related to ESR value of output capacitor UJA1069_3 Product data sheet stable operation area 2 10 unstable operation area Rev. 03 — 10 ...
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NXP Semiconductors a. Test circuit V (V) b. Behavior (V) c. Behavior at T Fig 23. Switch-on behavior of V UJA1069_3 Product data sheet BAT42 BAT14 100 F/ V BAT 0.1 100 ...
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NXP Semiconductors 10. Dynamic characteristics Table 26. Dynamic characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol ...
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NXP Semiconductors Table 26. Dynamic characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter t TXDL ...
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NXP Semiconductors Table 26. Dynamic characteristics +150 5 BAT42 voltages are defined with respect to ground. Positive currents flow into the IC. Symbol Parameter Interrupt output; ...
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NXP Semiconductors Fig 25. Timing test circuit for LIN transceiver t bit V TXDL V BAT42 LIN BUS signal V RXDL1 receiving node 1 t p(rx)f V RXDL2 receiving node 2 Fig 26. Timing diagram LIN transceiver 11. Test information ...
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NXP Semiconductors 12. Package outline HTSSOP32: plastic thermal enhanced thin shrink small outline package; 32 leads; body width 6.1 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad side pin 1 index 1 ...
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NXP Semiconductors HTSSOP24: plastic thermal enhanced thin shrink small outline package; 24 leads; body width 4.4 mm; lead pitch 0.65 mm; exposed die pad y exposed die pad Z 24 pin 1 index 1 e DIMENSIONS (mm are the original ...
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NXP Semiconductors 13. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 13.1 Introduction to soldering Soldering ...
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NXP Semiconductors 13.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...
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NXP Semiconductors Fig 29. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 14. Revision history Table 29. Revision history Document ID Release date UJA1069_3 ...
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NXP Semiconductors 15. Legal information 15.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...
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NXP Semiconductors 17. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...