HCTL-2032 Avago Technologies US Inc., HCTL-2032 Datasheet - Page 15

• Manufacturer Part Number: HCTL-2032
• Description: IC QUAD DECODER/COUNTER 32DIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2032

• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 32-DIP (0.600", 15.24mm)
• Mounting Type: Through Hole
• Current, Supply: 1 μA
• Function Type: 32-Bits
• Logic Function: Counter/Decoder
• Logic Type: CMOS/LSTLL
• Number Of Circuits: Dual
• Package Type: PDIP-32
• Special Features: Binary, Bus, Schmitt-Trigger, Tri-State
• Temperature, Operating, Range: -40 to +100 °C
• Voltage, Supply: 4.5 to 5.5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: Q2414340

Figure 14. 2x and 1x Decoder Modes
Design Considerations
The designer should be aware that the operation of the
digital filter places a timing constraint on the relationship
between incoming quadrature signals and the external
clock. Figure 12 shows the timing waveform with an in-
cremental encoder input. Since an input has to be stable
for three rising clock edges, the encoder pulse width (t
- low or high) has to be greater than three clock periods
(3t
be stable during three consecutive rising clock edges. A
realistic design also has to take into account finite rise
time of the waveforms, asymmetry of the waveforms,
and noise. In the presence of large amounts of noise, t
should be much greater than 3t
ruption of the consecutive level sampling by the three-
bit delay filter. It should be noted that a change on the
inputs that is qualified by the filter will internally propa-
gate in a maximum of seven clock periods.
The quadrature decoder circuitry imposes a second tim-
ing constraint between the external clock and the input
signals. There must be at least one clock period between
consecutive quadrature states. As shown in Figure 13,
a quadrature state is defined by consecutive edges on
both channels. Therefore, t
t
nominal 90 degree phasing of input signals to guarantee
that t

Figure 13. 4x Decoder Mode
CLK
CHA


0
0
CHA


0
0
CLK
. The designer must account for deviations from the
ES
). This guarantees that the asynchronous input will
> t
CLK
CHB
0


0
CHB
0


0
.
STATE


3
4
STATE


3
4
ES
(encoder state period) >
CLK
2x
Count Up
Pulse
-
Pulse
-
4X Decoder
(Count Up & Count Down)
Pulse
Pulse
Pulse
Pulse
to allow for the inter-
2x
Count Down
-
Pulse
-
Pulse
E
E
Position Counter
This section consists of a 32-bit (HCTL-20XX-XX) binary
up/down counter which counts on rising clock edges as
explained in the Quadrature Decoder Section. All 32 bits
of data are passed to the position data latch. The system
can use this count data in several ways:
A. System total range is 32 bits, so the count represents
B. The system is cyclic with 32 bits of count per cycle.
C. System count is >8, 16, 24, or 32 bits, so the count data
D. The system count is >32 bits so the HCTL-2032 / 2032-
“absolute” position.
RST/ is used to reset the counter every cycle and the
system uses the data to interpolate within the cycle.
is used as a relative or incremental position input for a
system software computation of absolute position. In
this case counter rollover occurs. In order to prevent
loss of position information, the processor must read
the outputs of the IC before the count increments
one-half of the maximum count capability. Two’s-
complement arithmetic is normally used to compute
position from these periodic position updates.
SC can be cascaded with other standard counter ICs to
give absolute position.
1x
Count Up
Pulse
-
-
-
1x
Count Down
-
Pulse
-
-